H5TQ4G43BMR-xxC

4Gb DDR3 SDRAM 4Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ4G43BMR-xxC H5TQ4G83BMR-xxC * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 0.2 / Jun. 2010 1 Revision History Revision No. 0.1 0.2 History Initial Release Corrected typo on row and column address table Draft Date Apr. 2010 Jun. 2010 Remark Rev. 0.2 / Jun. 2010 2 Description The H5TQ4G43BMR-xxC, H5TQ4G83BMR-xxC are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES VDD=VDDQ=1.5V +/- 0.075V Fully differential clock inputs (CK, CK) operation 8banks Average Refresh Cycle (Tcase of 0 oC~ 95 oC) Differential Data Strobe (DQS, DQS) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC On chip DLL align DQ, DQS and DQS transition with CK  transition Auto Self Refresh supported DM masks write data-in at the both rising and falling  edges of the data strobe All ...