MT41K512M8

4Gb: x4, x8, x16 DDR3L SDRAM Description DDR3L SDRAM MT41K1G4 – 128 Meg x 4 x 8 banks MT41K512M8 – 64 Meg x 8 x 8 banks MT41K256M16 – 32 Meg x 16 x 8 banks Description DDR3L SDRAM (1.35V) is a low voltage version of the DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM (Die Rev :E) data sheet specifications when running in 1.5V compatible mode. Features VDD = VDDQ = 1.35V (1.283–1.45V) Backward compatible to VDD = VDDQ = 1.5V ±0.075V – Supports DDR3L devices to be backward compatible in 1.5V applications Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS (READ) latency (CL) Programmable posted CAS additive latency (AL) Programmable CAS (WRITE) latency (CWL) Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Self refresh mode TC of 105°C – 64ms, 8192-cycle refresh up to 85°C – 32ms, 8192-cycle refresh at >85°C to 95°C – 16ms, 8192-cycle refresh at >95°C to 105°C Self refresh temperature (SRT) Automatic self refresh (ASR) Write leveling Multipurpose register Output driver calibration Options Configuration – 1 Gig x 4 – 512 Meg x 8 – 256 Meg x 16 FBGA package (Pb-free) – x4, x8 – 78-ball (9mm x 10.5mm) Rev. E – 78-ball (7.5mm x 10.6mm) Rev. N – 78-ball (8mm x 10.5mm) Rev. P FBGA package (Pb-free) ...