Document
4Gb: x4, x8 TwinDie DDR2 SDRAM Features
TwinDie™ DDR2 SDRAM
MT47H1G4 – 64 Meg x 4 x 8 Banks x 2 Ranks MT47H512M8 – 32 Meg x 8 x 8 Banks x 2 Ranks Features
• Uses 2Gb Micron die • Two ranks (includes dual CS#, ODT, and CKE balls) • Each rank has 8 internal banks for concurrent operation • VDD = V DDQ = +1.8V ±0.1V • JEDEC-standard 63-ball FBGA • Low-profile package – 1.35mm MAX thickness Functionality The 4Gb (TwinDie™) DDR2 SDRAM uses Micron’s 2Gb DDR2 monolithic die and has similar functionality. This TwinDie data sheet is intended to provide a general description, package dimensions, and the ballout only. Refer to Micron's 2Gb DDR2 data sheet for complete information or for specifications not included in this document.
Options
• Configuration – 64 Meg x 4 x 8 banks x 2 ranks – 32 Meg x 8 x 8 banks x 2 ranks • FBGA package (Pb-free) – 63-ball FBGA (9mm x 11.5mm) Rev. C • Timing – cycle time1 – 2.5ns @ CL = 5 (DDR2-800) – 2.5ns @ CL = 6 (DDR2-800) – 3.0ns @ CL = 5 (DDR2-667) – 3.75ns @ CL = 4 (DDR2-533) • Self refresh – Standard • Operating temperature – Commercial (0°C ≤ T C ≤ 85°C) • Revision
Note: 1. CL = CAS (READ) latency.
Marking
1G4 512M8 WTR -25E -25 -3 -37E None None :C
Table 1: Key Timing Parameters
Speed Grade -25E -25 -3 -37E Data Rate (MT/s) CL = 3 400 400 400 400 CL = 4 533 533 533 533 CL = 5 800 667 667 n/a CL = 6 800 800 n/a n/a
tRCD tRP tRC tRFC
(ns)
(ns)
(ns)
(ns)
12.5 15 15 15
12.5 15 15 15
55 55 55 55
197.5 197.5 197.5 197.5
Table 2: Addressing
Parameter Configuration Refresh count Row address Bank address Column address 1 Gig x 4 64 Meg x 4 x 8 banks x 2 ranks 8K A[14:0] (32K) BA[2:0] (8) A[11, 9:0] (2K) 512 Meg x 8 32 Meg x 8 x 8 banks x 2 ranks 8K A[14:0] (32K) BA[2:0] (8) A[9:0] (1K)
PDF: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
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Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 63-Ball FBGA – x4, x8 Ball Assignments (Top View)
1 A B C D E
VDDL VDDQ NF, DQ4
2
3
4
5
6
7
8
9
VDD NF, NU/RDQS# VSS NF, DQ6
VSSQ DQS
DQS#/NU VDDQ VSSQ DQ0 NF, DQ7
VSSQ DM, RDQS DQ1
VDDQ DQ3
VDDQ DQ2
VDDQ NF, DQ5
VSSQ VREF CKE0
VSSQ CK
VSS WE#
VSSDL RAS#
VDD ODT0
F
CK#
G
BA2
BA0
BA1
CAS#
CS0#
CS1#
H J K L
CKE1
A10
A1
A2
A0
VDD ODT1
VSS
A3
A5
A6
A4
A7
A9
A11
A8
VSS
VDD
A12
A14
RFU
A13
Note:
1. Dark balls (with ring) designate balls that differ from the monolithic versions.
PDF: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM Ball Assignments and Descriptions
Table 3: FBGA 63-Ball Descriptions
Symbol A[14:0] Type Input Description Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Bank address inputs: BA[2:0] define to which bank an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE power-down (row active in any bank). CKE is synchronous for power-down entry, powerdown exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level once VDD is applied during first power-up. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH operation, VREF must be maintained. Chip select: CS# enables (registered LOW) and disables (registered HIG.