MT46H8M32LG

256Mb: x16, x32 Mobile DDR SDRAM Features Mobile DDR SDRAM MT46H16M16LF – 4 Meg x 16 x 4 banks MT46H8M32LF/LG – 2 Meg x 32 x 4 banks For the latest data sheet, refer to Micron’s Web site: www.micron.com Features Endur-IC™ technology VDD/VDDQ = 1.70–1.95V Bidirectional data strobe per byte of data (DQS) Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs Four internal banks for concurrent operation Data masks (DM) for masking write data—one mask per byte Programmable burst lengths: 2, 4, or 8 Concurrent auto precharge option supported Auto refresh and self refresh modes 1.8V LVCMOS compatible inputs On-chip temperature sensor to control self refresh rate Partial-array self refresh (PASR) Deep power-down (DPD) Selectable output drive (DS) Clock stop capability 64ms refresh period (8,192 rows) Configuration Addressing JEDECStandard Option 4 BA0, BA1 A0–A12 A0–A8 A0–A11 A0–A8 Reduced Page-Size Option 4 BA0, BA1 – – A0–A12 A0–A7 Table 2: Speed Grade -6 -75 Key Timing Parameters Clock Rate (MHz) CL = 2 83.3 83.3 CL = 3 166 133 Access Time CL = 2 6.5ns 6.5ns CL = 3 5.0ns 6.0ns Options VDD/VDDQ – 1.8V/1.8V Configuration – 16 Meg x 16 (4 Meg x 16 x 4 banks) – 8 Meg x 32 (2 Meg x 32 x 4 banks) Row size option – JEDEC-standard option – Reduced page-...