Mobile SDRAM
64Mb: 4 Meg x 16 Mobile SDRAM Features
Mobile SDRAM
MT48H4M16LF – 1 Meg x 16 x 4 banks
Features
• 1.70–1.95V • Fully s...
Description
64Mb: 4 Meg x 16 Mobile SDRAM Features
Mobile SDRAM
MT48H4M16LF – 1 Meg x 16 x 4 banks
Features
1.70–1.95V Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or continuous page1 Auto precharge, includes concurrent auto precharge Self refresh mode 64ms, 4,096-cycle refresh LVTTL-compatible inputs and outputs Partial-array self refresh (PASR) power-saving mode On-die temperature-compensated self refresh (TCSR) Deep power-down (DPD) mode Programmable output drive strength Operating temperature ranges – Commercial (0°C to +70°C) – Industrial (–40°C to +85°C) Notes: 1. For continuous page burst, contact factory for availability.
Figure 1:
54-Ball VFBGA Ball Assignment (Top View)
2
DQ15
1 A B C D E F G H J
VSS
3
VSSQ
4
5
6
7
VDDQ
8
DQ0
9
VDD
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
DQ8
NC
VSS
VDD
LDQM
DQ7
UDQM
CLK
CKE
CAS#
RAS#
WE#
NC
A11
A9
BA0
BA1
CS#
A8
A7
A6
A0
A1
A10
VSS
A5
A4
A3
A2
VDD
Top view (Ball down)
Table 1:
Address Table
4 Meg x 16
Options
VDD/VDDQ – 1.8V/1.8V Configurations – 4 Meg x 16 (1 Meg x 16 x 4 banks) Plastic “green” package – 54-ball VFBGA, 8mm x 8mm Timing (cycle time) – 7.5ns @ CL = 3 (133 MHz) – 8ns @ CL = 3 (125 MHz) Operating ...
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