AS8C401800

128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect ◆ ◆ AS8C403600 AS8C401800 Features 128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial: – 150MHz 3.8ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control ( GW l ( ), byte write enable (BWE), and byte writes ( BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O Optional - Boundary Scan JTAG Interface (IEEE 1149.1 compliant) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP). Description ◆ ◆ ◆ ◆ ◆ ◆ ◆ TheAS8C403600/1800 are high- speed SRAMs organized as 128K x 36/256K x 18. The AS8C403600/401800 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer,as theAS8C403600/1800 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (A ( DV=LOW), the subsequent three cycles of output data will be available to the user on the next...