Document
Integrated Power Solution with Quad Buck Regulators, Supervisory Circuit, and I2C Interface
Data Sheet
FEATURES
Wide input voltage range: 4.5 V to 15.0 V ±1.5% output accuracy over full temperature range 250 kHz to 1.4 MHz adjustable switching frequency Adjustable/fixed output options via factory fuse or I2C interface I2C interface with interrupt on fault conditions Power regulation Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A sync buck regulators with low-side FET driver Channel 3 and Channel 4: 1.2 A sync buck regulators Single 8 A output (Channel 1 and Channel 2 in parallel) Dynamic voltage scaling (DVS) for Channel 1 and Channel 4 Precision enable with 0.8 V accurate threshold Active output discharge switch Programmable phase shift in 90° steps Individual channel FPWM/PSM selection Frequency synchronization input or output Optional latch-off protection on OVP/OCP failure Power-good flag on selected channels Low input voltage detection Open-drain processor reset with external adjustable threshold monitoring Watchdog refresh input Manual reset input Overheat detection on junction temperature UVLO, OCP, and TSD protection
C1 C0 FB1 PVIN1
ADP5051
TYPICAL APPLICATION CIRCUIT
ADP5051
VREG VDD SYNC/MODE RT
INT VREG OSCILLATOR 100mA
4.5V TO 15V C2
COMP1 EN1 SS12 CHANNEL 1 BUCK (4A) VREG
BST1 SW1 C3
L1
VOUT1 C4
DL1 PGND DL2 RILIM1 RILIM2
Q1
C5
PVIN2 COMP2 EN2
Q2 CHANNEL 2 BUCK (4A) VREG SW2 BST2 FB2 C6 L2 VOUT2 C7
PVIN3 C8 COMP3 EN3 SS34 CHANNEL 3 BUCK (1.2A)
BST3 C9 SW3 FB3 PGND3 BST4 L3 VOUT3 C10
PVIN4 C11 COMP4 EN4 WDI MR CHANNEL 4 BUCK (1.2A) SW4 FB4 PGND4 RSTO WATCHDOG AND RESET VTH
C12
L4
VOUT4 C13
VREG
VOUTx
VDDIO SCL SDA
I2C
ALERT
PWRGD INT
11635-001
EXPOSED PAD
Figure 1.
APPLICATIONS
Small cell base stations FPGA and processor applications Security and surveillance Medical applications
Combining Channel 1 and Channel 2 in a parallel configuration provides a single output with up to 8 A of current. Channel 3 and Channel 4 integrate both high-side and low-side MOSFETs to deliver an output current of 1.2 A. The ADP5051 supervisory circuits monitor the voltage level. The watchdog timer generates a reset when the WDI pin does not toggle within a preset timeout period. Select manual reset functionality via the processor reset mode or system power on/off switch mode. The optional I2C interface offers flexible configurations, including adjustable and fixed output voltage, junction temperature overheat warning, low input voltage detection, and dynamic voltage scaling. Table 1. Family Models
Model ADP5050 ADP5051 ADP5052 ADP5053 Channels Four bucks, one LDO Four bucks, supervisory Four bucks, one LDO Four bucks, supervisory I2C Yes Yes No No Package 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP
GENERAL DESCRIPTION
The ADP5051 combines four high performance buck regulators and a supervisory circuit with a voltage monitor, a watchdog function, and a manual reset in a 48-lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input voltages up to 15.0 V with no preregulators. Channel 1 and Channel 2 integrate high-side power MOSFET and low-side MOSFET drivers. In low-side power devices, use external NFETs to achieve an efficiency optimized solution and deliver a programmable output current of 1.2 A, 2.5 A, or 4 A.
Rev. 0
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ADP5051 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Buck Regulator Specifications .................................................... 6 Supervisory Specifications .......................................................... 8 I C Interface Timing Specifications .................