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SAF82520 Dataheets PDF



Part Number SAF82520
Manufacturers Siemens
Logo Siemens
Description High-Level Serial Communications Controller
Datasheet SAF82520 DatasheetSAF82520 Datasheet (PDF)

High-Level Serial Communications Controller (HSCC) 1 Features Two independent HDLC channels Implementation of X.25 LAPB/LAPD protocol Programmable timeout and retry conditions FIFO buffers for efficient transfer of data packets Digital phase-locked loop for each channel Baudrate generator and oscillator Different modes for clock recovery and data encoding High-speed data rate (up to 4 MHz) Supports bus configuration by collision resolution Telecom-specific features programmable 8-bit parallel µP.

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High-Level Serial Communications Controller (HSCC) 1 Features Two independent HDLC channels Implementation of X.25 LAPB/LAPD protocol Programmable timeout and retry conditions FIFO buffers for efficient transfer of data packets Digital phase-locked loop for each channel Baudrate generator and oscillator Different modes for clock recovery and data encoding High-speed data rate (up to 4 MHz) Supports bus configuration by collision resolution Telecom-specific features programmable 8-bit parallel µP interface Advanced CMOS technology Low power consumption; active: 25 mW at 4 MHz standby: 3 mW SAB 82520: operating temperature 0 to 70 ˚C SAF 82520: operating temperature – 40 to 85 ˚C SAB 82520 SAF 82520 P-LCC-28-R P-DIP-28 SAB 82520, a High-level Serial Communications Controller (HSCC), has been designed to free the user from tasks occurring in communication via networks and trunk lines. SAB 82520 is an X.25 LAPB/LAPD controller which, to a large degree performs communications procedures independently of CPU support. A parallel processor bus constitutes the µC system. The communications interface is implemented by two full-duplex HDLC channels, which can be operated independently from one another. The HSCC is connected to the transmission line via additional line drivers or modems. External logic is cost-effective because clock recovery can be performed by an onchip oscillator, DPLL circuits and a programmable baudrate generator. Type SAB 82520-N SAB 82520-P SAF 82520-N SAF 82520-P Ordering Code Q67100-H8400 Q67100-H8014 Q67100-H8610 Q67100-H8512 Package P-LCC-28 (SMD) P-DIP-28 P-LCC-28 (SMD) P-DIP-28 Semiconductor Group 5 03.94 SAB 82520 SAF 82520 Figure 1 Logic Symbol Semiconductor Group 6 SAB 82520 SAF 82520 Pin Configurations (top view) P-DIP P-LCC Figure 2 Semiconductor Group 7 SAB 82520 SAF 82520 1.1 Pin Definitions and Functions Pin No. Symbol 25 26 27 28 1 2 3 4 5 12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 RTSA RTSB Input (I) Output (O) I/O I/O I/O I/O I/O I/O I/O I/O O O Functions Address Data Bus The multiplexed address data bus transfers data and commands between the µP system and the HSCC. Request to Send When the RTS bit in MODE is set, the RTS signal goes low. When the RTS bit is reset, the signal goes high of the transmitter has finished and there is no further request for a transmission. In a bus configuration, RTS goes low during the actual transmission of a frame shifted by a clock period, excluding collision bits. Clear to Send/Collision Data A low on the inputs enables the respective transmitter. If the transmitters are always enabled, CTS should be connected to VSS. In a bus configuration the external serial bus must be connected to the respective C ¥ D pin. Receive Data These lines receive serial data at standard TTL or CMOS levels. Transmit Data These lines transmit serial data at standard TTL or CMOS levels. They can be programmed as push-pull or open-drain outputs. RESET A high on this input forces the HSCC into reset state. The HSCC is in power-up mode during reset and in power-down mode after reset. The minimum pulse length is 1.8 µs. Ground (0 V) Interrupt Request The signal is activated when the HSCC requests an interrupt. It is an open-drain output. 6 11 CTSA/C × DA CTSA/C × DA I I 7 10 8 9 R × DA R × DB T × DA T × DB I I O O 13 RES I 14 15 VSS INT O Semiconductor Group 8 SAB 82520 SAF 82520 Pin Definitions and Functions (cont’d) Pin No. Symbol 16 ALE Input (I) Output (O) I Functions Address Latch Enable A high on this line indicates an address on the external address data bus, selecting one of the HSCC internal sources or destinations. Chip Select A low on this signal selects the HSCC for a read/write operation. Transmit Clock These pins can be programmed in several different modes of operation. T × CLK may supply the transmit clock for the respective channel, a receive strobe signal (T × CLK A) and a transmit strobe signal (T × CLK B) or a frame synchronization signal (T × CLK A, clock mode 5). Programmed as outputs, T × CLK supply the transmit clock of the respective channel or a tristate control signal, indicating the programmed transmit time slot (T × CLK B, clock mode 5). Receive Clock These pins can be programmed in several different modes of operation. In each channel R × CLK may supply the receive clock, the receive and transmit clock, the clock for the baud rate generator or the clock for the DPLL. They also can be programmed for use as a crystal oscillator. Power + 5 V power supply. I I Write This signal indicates a write operation. Read This signal indicates a read operation. 17 CS I 18 19 T × CLK B T × CLK A I/O I/O 20 21 R × CLK B R × CLK A I I 22 23 24 VDD WR RD Semiconductor Group 9 SAB 82520 SAF 82520 1.2 Functional Description In a point-to-multipoint or in a multimaster configuration the HSCC can be used as a central station (master) or a peripheral station. As a peripheral station the HSCC can initiate the transmission of d.


SAB82520 SAF82520 SAB82520-N


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