Document
P-Channel Enhancement Mode MOSFET
Product Summary
VDS (V) ID (A)
RDS(ON) (mΩ) Max 40 @VGS = - 10V -30V -20A 65 @VGS = - 5V 75 @VGS = - 4.5V
G S D
SSD2030P
TO-252
D
FEATURES
Super high density cell design for low RDS(ON). Rugged and reliable. TO-252 package. Pb free.
G S
ABSOLUTE MAXIMUM RATINGS (TA = 25 C unless otherwise noted)
Parameter
Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous @ TJ = 125 C -Pulsed
b o
o
Symbol
VDS VGS ID IDM
a
Limit
-30 + - 25 -20 -50 -1.7 50 -55 to 150
Unit
V V A A A W
o
Drain-Source Diode Forward Current Maximum Power Dissipation
a
IS PD TJ, TSTG
Operating Junction and Storage Temperature Range
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient
a
R R
JC JA
3 50
o
C/W
South Sea Semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. South Sea Semiconductor, January 2008 (Rev 2.1)
1
SSD2030P
P-Channel Electrical Characteristics (TA = 25 C unless otherwise noted)
Parameter
Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate-Body Leakage Gate Threshold Voltage
o
Symbol
BVDSS IDSS IGSS VGS(th)
Condition
VGS=0V, ID=-250 A
Min
-30
Typ
c
Max
Unit
V
VDS=-24V, VGS=0V VGS= 25V, VDS=0V -1 -1.9 35 60 70 -35 10 700 130 90 10 8 40 30 16 9 3 3.5 -0.85
-1 100 -2.5 40 65 75
A nA V
VDS=VGS ID= -250 A VGS= -10V, ID = -20A
Drain-Source On-State Resistance
RDS(ON)
VGS= -5V, I D = -10A VGS=-4.5V, ID= - 10A
m
On-State Drain Current Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Diode Forward Voltage
ID(ON) gFS CISS COSS CRSS tD(ON) tr tD(OFF) tf Qg Qgs Qgd VSD
VDS= -5V, VGS= -10V VDS= -5V, I D = -5.3A VDS= -15V VGS=0V f=1.0MHz VDD= -15V, ID= -1A, VGEN= -10V, RGEN=6 ,
A S 800
PF
ns
VDS=-15V, ID=-5.3A, VGS=-10V VDS=-15V, ID=-5.3A, VGS=-4.5V
20 nC
VDS= -15V, ID = -6A, VGS=-10V VGS=0V, ID=-1.0A
-1.2
V
Notes a. Surface Mounted on FR4 Board, t <10 - sec. b. Pulse Test Pulse Width < 300 s, Duty Cycle < - 2%. c. Guaranteed by design, not subject to production testing.
South Sea Semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. South Sea Semiconductor, January 2008 (Rev 2.1)
2
SSD2030P
10 8 -VGS = 10.5V~2.5V 20 25 C
o
-ID, Drain Current (A)
-ID, Drain Current (A)
16
6
12
4
8
2
4
-VGS = 1.5V 0 0 2 4 6 8 10 12 0 0.5 1.0
Tj = 125 C
o
0
-55 C
1.5 2.0 2.5 3.0
o
-VDS, Drain-to-Source Voltage (V)
-VGS, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
Figure 2. Thansfer Characteristics
1200
1.8
800 600 400 200 0 0 5
Ciss
RDS(ON), On-Resistance Normalized ( )
1000
1.6 1.4 1.2 1.0 0.8 0.6
VGS = -10V ID = -5.8A
C, Capacitance (pF)
Coss Crss
10 15 20 25 30
-55
-25
0
25
50
75
100
125
-VDS, Drain-to-Sou.