P4004ED

NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor D P4004ED TO-252(DPAK) Halogen-Free & Lead-Free PRODUCT SUMMARY V(BR)DSS -40V RDS(ON) 40mΩ ID -21A G S 1. GATE 2. DRAIN 3. SOURCE ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Avalanche Current Avalanche Energy Power Dissipation Junction & Storage Temperature Range 2 1 SYMBOL VDS VGS LIMITS -40 ±20 -21 -17 -70 -27 36 30 20 UNITS V V TC = 25 °C TC = 70 °C ID IDM IAS A L = 0.1mH TC = 25 °C TC = 70 °C EAS PD TJ, Tstg mJ W °C -55 to 150 THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 2 SYMBOL RθJc RθJA TYPICAL MAXIMUM 4.1 40 UNITS °C / W °C / W Pulse width limited by maximum junction temperature. VDD = -20V . Starting TJ = 25˚C. ELECTRICAL CHARACTERISTICS (TJ = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current REV 1.1 1 1 LIMITS UNIT MIN TYP MAX V(BR)DSS VGS(th) IGSS IDSS ID(ON) VGS = 0V, ID = -250µA VDS = VGS, ID = -250µA VDS = 0V, VGS = ±20V VDS = -32V, VGS = 0V VDS = -30V, VGS = 0V, TJ = 125 °C VDS = -5V, VGS = -10V -40 -2.0 -2.5 -3 V ±250 nA 1 10 µA A Sep-16-2010 -70 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor VGS = -5V, ID = -8A P4004ED...