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PMK35EP Dataheets PDF



Part Number PMK35EP
Manufacturers NXP Semiconductors
Logo NXP Semiconductors
Description P-channel TrenchMOS extremely low level FET
Datasheet PMK35EP DatasheetPMK35EP Datasheet (PDF)

PMK35EP P-channel TrenchMOS extremely low level FET Rev. 02 — 29 April 2010 Product data sheet 1. Product profile 1.1 General description Extremely low level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits  Low conduction losses due to low on-state resistance 1.3 Applications  Battery manag.

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PMK35EP P-channel TrenchMOS extremely low level FET Rev. 02 — 29 April 2010 Product data sheet 1. Product profile 1.1 General description Extremely low level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits  Low conduction losses due to low on-state resistance 1.3 Applications  Battery management  Load switching 1.4 Quick reference data Table 1. Symbol VDS ID Ptot Quick reference data Parameter drain-source voltage drain current total power dissipation drain-source on-state resistance Conditions 25 °C ≤ Tj ≤ 150 °C Tsp = 25 °C; VGS = -10 V; see Figure 1; see Figure 3 Tsp = 25 °C; see Figure 2 Min Typ Max Unit -30 -14. 9 6.9 V A W Static characteristics RDSon VGS = -10 V; ID = -9.2 A; Tj = 25 °C; see Figure 9 16 19 mΩ Dynamic characteristics QGD gate-drain charge VGS = -10 V; ID = -9.2 A; VDS = -15 V; Tj = 25 °C; see Figure 11; see Figure 12 6 nC NXP Semiconductors PMK35EP P-channel TrenchMOS extremely low level FET 2. Pinning information Table 2. Pin 1 2 3 4 5 6 7 8 Pinning information Symbol Description S S S G D D D D source source source gate drain drain drain drain 1 4 S 001aaa025 Simplified outline 8 5 Graphic symbol D G SOT96-1 (SO8) 3. Ordering information Table 3. Ordering information Package Name PMK35EP SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 Type number 4. Limiting values Table 4. Symbol VDS VDGR VGS ID Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current Tsp = 25 °C; VGS = -10 V; see Figure 1; see Figure 3 Tsp = 100 °C; VGS = -10 V; see Figure 1 IDM Ptot Tstg Tj IS ISM peak drain current total power dissipation storage temperature junction temperature source current peak source current Tsp = 25 °C Tsp = 25 °C; tp ≤ 10 µs; pulsed Tsp = 25 °C; tp ≤ 10 µs; pulsed; see Figure 3 Tsp = 25 °C; see Figure 2 Conditions 25 °C ≤ Tj ≤ 150 °C 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ Min -25 -55 -55 Typ Max -30 -30 25 -14.9 -7 -28.8 6.9 150 150 -5.8 -23 Unit V V V A A A W °C °C A A In accordance with the Absolute Maximum Rating System (IEC 60134). Source-drain diode PMK35EP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 29 April 2010 2 of 12 NXP Semiconductors PMK35EP P-channel TrenchMOS extremely low level FET 120 Ider (%) 80 003aab604 120 Pder (%) 80 003aab948 40 40 0 0 50 100 150 Tj (°C) 200 0 0 50 100 150 Tsp (°C) 200 Fig 1. Normalized continuous drain current as a function of solder point temperature Fig 2. Normalized total power dissipation as a function of solder point temperature 003aab603 −102 Limit RDSon = VDS / ID ID (A) −10 1 ms tp = 10 μs 10 ms −1 DC 100 ms −10−1 −10−1 −1 −10 VDS (V) −102 Tsp = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 5. Thermal characteristics Table 5. Symbol Rth(j-sp) Thermal characteristics Parameter thermal resistance from junction to solder point Conditions see Figure 4 Min Typ Max 18 Unit K/W PMK35EP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 29 April 2010 3 of 12 NXP Semiconductors PMK35EP P-channel TrenchMOS extremely low level FET 102 Zth(j−sp) (K / W) 10 δ = 0.5 0.2 0.1 1 0.05 0.02 P 003aab605 δ= tp T 10−1 single pulse tp t T 10−2 10−4 10−3 10−2 10−1 1 tp (s) 10 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration 6. Characteristics Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = -250 µA; VGS = 0 V; Tj = 25 °C ID = -250 µA; VGS = 0 V; Tj = -55 °C ID = -250 µA; VDS = VGS; Tj = 25 °C; see Figure 7; see Figure 8 ID = -250 µA; VDS = VGS; Tj = 150 °C; see Figure 7; see Figure 8 ID = -250 µA; VDS = VGS; Tj = -55 °C; see Figure 7; see Figure 8 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = -30 V; VGS = 0 V; Tj = 25 °C VDS = -30 V; VGS = 0 V; Tj = 70 °C VGS = 20 V; VDS = 0 V; Tj = 25 °C VGS = -20 V; VDS = 0 V; Tj = 25 °C VGS = -10 V; ID = -9.2 A; Tj = 25 °C; see Figure 9 VGS = -10 V; ID = -9.2 A; Tj = 150 °C; see Figure 9 VGS = -4.5 V; ID = -6.8 A; Tj = 25 °C; see Figure 10; see Figure 9 Dynamic characteristics QG(tot) QGS QGD total gate charge gate-source charge gate-drain charge ID = -9.2 A; VDS = -15 V; VGS = -10 V; Tj = 25 °C; see Figure 11; see Figure 12 42 8 6 nC nC nC Min -30 -27 -1 -0.7 Typ 16 25 26 Max -3 -3.3 -1 -10 -100 -100 19 31 35 Unit V V V V V µA µA nA nA mΩ mΩ mΩ Static characteristics PMK35EP All information provided in this document is subjec.


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