SPP3401D

SPP3401D P-Channel Enhancement Mode MOSFET DESCRIPTION The SPP3401D is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density , DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits, and low in-line power loss are needed in a very small outline surface mount package. APPLICATIONS  Power Management in Note book  Portable Equipment  Battery Powered System  DC/DC Converter  Load Switch  DSC  LCD Display inverter FEATURES  -30V/-4.0A,RDS(ON)=70mΩ@VGS=-10V  -30V/-3.2A,RDS(ON)=90mΩ@VGS=-4.5V  -30V/-1.2A,RDS(ON)=115mΩ@VGS=-2.5V  Super high density cell design for extremely low RDS(ON)  Exceptional on-resistance and maximum DC current capability  SOT-23 package design PIN CONFIGURATION(SOT-23) 2020/1/15 Ver.2 PART MARKING S41YW Page 1 SPP3401D P-Channel Enhancement Mode MOSFET PIN DESCRIPTION Pin 1 2 3 Symbol G S D Description Gate Source Drain ORDERING INFORMATION Part Number Package SPP3401DS23RGB SOT-23 ※ Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 ) ※ SPP3401DS23RGB : Tape Reel ; Pb – Free; Halogen – Free Part Marking S41 ABSOULTE MAXIMUM RATINGS (TA=25℃ Unless otherwise noted) Parameter Drain-Source Voltage Gate –Source Voltage Continuous Drain Current(TJ=150℃) Pulsed Drain Current TA=...