Octal Bus Transceivers (with 3-state outputs)
HD74HCT640/HD74HCT643
Octal Bus Transceivers (with 3-state outputs)
Description
Both the HD74HCT640 and the HD74HCT643 ...
Description
HD74HCT640/HD74HCT643
Octal Bus Transceivers (with 3-state outputs)
Description
Both the HD74HCT640 and the HD74HCT643 have one active low enable input (G ), and a direction control (DIR). When the DIR input is high, data flows from the A inputs to the B outputs. When DIR is low, data flows from B to A. The HD74HCT640 transfers inverted data from one bus to the other. The HD74HCT643 transfers inverted data from the A bus to the B bus and non-inverted data from the B bus to the A bus.
Features
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A to B) = 14.5 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Control Input G L L H DIR L H X Operation HD74HCT640 B data to A bus A data to B bus Isolation HD74HCT643 B data to A bus A data to B bus Isolation
HD74HCT640/HD74HCT643
Pin Arrangement
HD74HCT640
DIR A1 A2 A3 A4 A5 A6 A7 A8
1 2 3 4 5 6 7 8 9
20 VCC 19 Enable G 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 B8 (Top view)
GND 10
2
HD74HCT640/HD74HCT643
HD74HCT643
DIR A1 A2 A3 A4 A5 A6 A7 A8
1 2 3 4 5 6 7 8 9
20 VCC 19 Enable G 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 B8 (Top view)
GND 10
Block Diagram
HD74HCT640
G DIR
VCC A B VCC
To 7 other inverters
To 7 other inverters
3
HD74HCT640/HD74HCT643
HD74HCT643
G DIR
VCC A B VCC
...
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