HD74HCT237

HD74HCT237 3-to-8-line Decoder/Demultiplexer with Address Latch Description The HD74HCT237 decodes a three-bit Address to one-of-eight active-high outputs. The device has a transparent latch for storage of the Address. Two Chip Selects, one active-low and one active-high, are provided to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and then by using one of the Chip Select as a data input while holding the other one active. The HD74HCT237 is the noninverting version of the HD74HCT137. Features LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A, B, C to Y) = 23 ns typ (C L = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HCT237 Function Table Inputs Enable GL X X L L L L L L L L H G1 X L H H H H H H H H H G2 H X L L L L L L L L L Select C X X L L L L H H H H X B X X L L H H L L H H X A X X L H L H L H L H X Outputs Y0 L L H L L L L L L L Y1 L L L H L L L L L L Y2 L L L L H L L L L L Y3 L L L L L H L L L L Y4 L L L L L L H L L L Y5 L L L L L L L H L L Y6 L L L L L L L L H L Y7 L L L L L L L L L H Output Corresponding to stored address L; all others H Pin Arrangement A B C GL G2 G1 Y7 GND 1 2 3 4 5 6 7 8 (Top view) B C GL G2 G1 Y7...