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MN103LF11Q Dataheets PDF



Part Number MN103LF11Q
Manufacturers Panasonic Semiconductor
Logo Panasonic Semiconductor
Description 32-bit Single-chip Microcontroller
Datasheet MN103LF11Q DatasheetMN103LF11Q Datasheet (PDF)

MN103L09/10/11/12/13/14/15/16/17/18/19/20/ 21/22/23/24/25/26/27 Series 32-bit Single-chip Microcontroller  Overview The MN103LF series of 32-bit single-chip microcomputers have multiple types of peripheral functions. This LSI series is well suited for camera, TV, VCR, AV, printer, telephone, FAX machine, air-conditioner, music instrument and other applications. This LSI series has flexible and optimized hardware configurations and simple efficient instruction set. This LSI series incorporates a.

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MN103L09/10/11/12/13/14/15/16/17/18/19/20/ 21/22/23/24/25/26/27 Series 32-bit Single-chip Microcontroller  Overview The MN103LF series of 32-bit single-chip microcomputers have multiple types of peripheral functions. This LSI series is well suited for camera, TV, VCR, AV, printer, telephone, FAX machine, air-conditioner, music instrument and other applications. This LSI series has flexible and optimized hardware configurations and simple efficient instruction set. This LSI series incorporates an internal ROM of 1048 KB (maximum) and RAM of 76 KB (maximum), 11 external interrupts, 96 internal interrupts including non-maskable interrupt, 26 timer counters, 14 sets of serial interfaces, A/D converter, D/A converter, 2 sets of watchdog timer, DMA, CAN, and IEBus interface. In addition, this LSI series has 5 oscillation circuits (external high frequency: 4 MHz to 20 MHz/ external low frequency:32.768 kHz/ internal high frequency: 20 MHz/ internal low frequency: 30 kHz/ PLL: frequency multiplier of high or low frequency). The internal clock can be switched to four oscillation clock except the internal low oscillation. The internal clock is generated by dividing the oscillation clock or PLL clock. The best operation clock for the system can be selected by switching its frequency ratio by programming. A machine cycle (minimum instruction execution time) is 25 ns (internal operating condition: 1.8 V, 40 MHz).  Product Summary This datasheet describes the following model. Series MN103L09 Model MN103LF09R MN103LF09Q MN103LF13R MN103LF13Q MN103LF10R MN103LF10Q MN103LF10N MN103LF10M MN103LF10K MN103LF14R MN103LF14Q MN103LF11R MN103LF11Q MN103LF11N MN103LF11M MN103LF11K MN103LF15R MN103LF15Q MN103LF12R MN103LF12Q MN103LF12N MN103LF19R MN103LF19Q MN103LF16R MN103LF16Q MN103LF16N MN103LF16M MN103LF16K Pin Number 144 ROM Size 1048 KB 792 KB 1048 KB 792 KB 1048 KB 792 KB 536 KB 408 KB 280 KB 1048 KB 792 KB 1048 KB 792 KB 536 KB 408 KB 280 KB 1048 KB 792 KB 1048 KB 792 KB 536 KB 1048 KB 792 KB 1048 KB 792 KB 536 KB 408 KB 280 KB RAM Size *1 76 KB 76 KB 64 KB 40 KB 32 KB 20 KB 76 KB 64 KB 40 KB 32 KB 20 KB 76 KB 64 KB 40 KB 76 KB 64 KB 40 KB 32 KB 20 KB  LQFP100-P-1414C LQFP144-P-2020D IEBus LQFP128-P-1818F LQFP100-P-1414C In-vehicle LAN CAN/IEBus Package LQFP144-P-2020D MN103L10/ MN103L13 100 MN103L11/ MN103L14 128 MN103L12/ MN103L15 144 MN103L16/ MN103L19 100 Note) *1: When using On-Chip Debug function, the debugger take over 500 Byte in size Publication date: February 2014 Ver. BEM 1 MN103L09/10/11/12/13/14/15/16/17/18/19/20/21/22/23/24/25/26/27 Series  Product Summary (continued) This datasheet describes the following model. Series Model MN103LF20R MN103LF20Q MN103LF17R MN103LF17Q MN103LF17N MN103LF17M MN103LF17K MN103LF21R MN103LF21Q MN103LF18R MN103LF18Q MN103LF18N MN103LF25R MN103LF25Q MN103LF22R MN103LF22Q MN103LF22N MN103LF22M MN103LF22K MN103LF26R MN103LF26Q MN103LF23R MN103LF23Q MN103LF23N MN103LF23M MN103LF23K MN103LF27R MN103LF27Q MN103LF24R MN103LF24Q MN103LF24N Pin Number ROM Size 1048 KB 792 KB 1048 KB 792 KB 536 KB 408 KB 280 KB 1048 KB 792 KB 1048 KB 792 KB 536 KB 1048 KB 792 KB 1048 KB 792 KB 536 KB 408 KB 280 KB 1048 KB 792 KB 1048 KB 792 KB 536 KB 408 KB 280 KB 1048 KB 792 KB 1048 KB 792 KB 536 KB RAM Size *1 76 KB 64 KB 40 KB 32 KB 20 KB 76 KB 64 KB 40 KB 76 KB 64 KB 40 KB 32 KB 20 KB 76 KB 64 KB 40 KB 32 KB 20 KB 76 KB 64 KB 40 KB LQFP144-P-2020D CAN LQFP128-P-1818F LQFP100-P-1414C LQFP144-P-2020D LQFP128-P-1818F  In-vehicle LAN Package MN103L17/ MN103L20 128 MN103L18/ MN103L21 144 MN103L22/ MN103L25 100 MN103L23/ MN103L26 128 MN103L24/ MN103L27 144 Note) *1: When using On-Chip Debug function, the debugger take over 500 Byte in size Ver. BEM 2 MN103L09/10/11/12/13/14/15/16/17/18/19/20/21/22/23/24/25/26/27 Series  Features  CPU core MN103L core (The instruction set is compatible MN103S series) Memory space 4 GB (instruct/data common use) LOAD-STORE architecture (3-stage pipeline) Machine cycle High-speed mode 25 ns/ 40 MHz (Max) Low-speed mode 30.3 ms/ 33 kHz (Max)  Operation mode NORMAL mode SLOW mode HALT mode STOP mode (CPU clock operation, Peripheral circuit clock operation mode) (CPU clock operation, Peripheral circuit clock operation mode) (CPU clock stop, Peripheral circuit clock operation mode) (All clocks stop mode)  Clock oscillation circuit : 5 circuits External high-speed oscillation (clkosc) External low-speed oscillation (clkx) Internal high-speed oscillation (clkrc) Internal low-speed oscillation (clkrcx) PLL output (clkpll) : Crystal oscillator/ Ceramic oscillator : 4 MHz to 20 MHz : Crystal oscillator/ Ceramic oscillator : 32.768 kHz : 20 MHz : 30 kHz : 60 MHz to 120 MHz  Clock multiple circuit (PLL) Multiplication rate : 4, 6, 8, 10, 12, 16, 20 multiplied clock of clkoscsel 2440 to 3660 multiplied clock of clkx Clock dividing : 2, 3 divided of clkpll PLL output dividing clock : 20 MHz to 40 MHz (clkplldiv)  Internal operation clock: 6 ty.


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