H9CKNNN8GTMPLR

168ball FBGA Specification 8Gb LPDDR3 (x32) This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.1 / Oct. 2013 1 H9CKNNN8GTMPLR LPDDR3-S8B 8Gb(x32) Document Title FBGA 8Gb (x32) LPDDR3 Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 1.1 - Initial Draft - Corrected tWLS and tWLH in AC Timing Parameters - Corrected a typo - Added DRAM speed 1866Mbps to ORDERING INFORMATION Final Version - Updated IDD specification and Input/Output Capacitance - Added DRAM speed 1866Mbps History Draft Date May. 2013 Jun. 2013 Jun. 2013 Jul. 2013 Aug. 2013 Oct. 2013 Remark Preliminary Preliminary Preliminary Preliminary Rev 1.1 / Oct. 2013 2 H9CKNNN8GTMPLR LPDDR3-S8B 8Gb(x32) FEATURES [ FBGA ] ● Operation Temperature - (-30)oC ~ 105oC ● Package - 168-ball FBGA - 12.0x12.0mm2, 0.70t, 0.50mm pitch - Lead & Halogen Free [ LPDDR3 ]  VDD1 = 1.8V (1.7V to 1.95V)  VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30)  HSUL_12 interface (High Speed Unterminated Logic 1.2V)  Double data rate architecture for command, address and data Bus; - all control and address except CS_n, CKE latched at both rising and falling edge of the clock - CS_n, CKE latched at rising edge of the clock - two data accesses per clock cycle  Differential clock inputs (CK_t, CK_c)  Bi-directional differential data strobe (DQS_t, DQS_c) - Source synchronous data transaction align...