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HD74ALVC16834 Dataheets PDF



Part Number HD74ALVC16834
Manufacturers Hitachi Semiconductor
Logo Hitachi Semiconductor
Description 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable
Datasheet HD74ALVC16834 DatasheetHD74ALVC16834 Datasheet (PDF)

HD74ALVC16834 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable ADE-205-216D (Z) 5th. Edition December 1999 Description The HD74ALVC16834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch enable ( LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is .

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HD74ALVC16834 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable ADE-205-216D (Z) 5th. Edition December 1999 Description The HD74ALVC16834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch enable ( LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip flop on the low to high transition of the CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to V CC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the driver. Features • Meets “PC SDRAM registered DIMM design support document, Rev. 1.2” • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±24 mA (@V CC = 3.0 V) HD74ALVC16834 Function Table Inputs OE H L L L L L L H: L: X: Z: ↑: Notes: LE X L L H H H H CLK X X X ↑ ↑ H L A X L H L H X X Output Y Z L H L H Y0 *1 Y0 *2 High level Low level Immaterial High impedance Low to high transition 1. Output level before the indicated steady-state input conditions were established, provided that CLK was high before LE went low. 2. Output level before the indicated steady-state input conditions were established. 2 HD74ALVC16834 Pin Arrangement NC 1 NC 2 Y1 3 GND 4 Y2 5 Y3 6 VCC 7 Y4 8 Y5 9 Y6 10 GND 11 Y7 12 Y8 13 Y9 14 Y10 15 Y11 16 Y12 17 GND 18 Y13 19 Y14 20 Y15 21 VCC 22 Y16 23 Y17 24 GND 25 Y18 26 OE 27 LE 28 (Top view) 56 GND 55 NC 54 A1 53 GND 52 A2 51 A3 50 VCC 49 A4 48 A5 47 A6 46 GND 45 A7 44 A8 43 A9 42 A10 41 A11 40 A12 39 GND 38 A13 37 A14 36 A15 35 VCC 34 A16 33 A17 32 GND 31 A18 30 CLK 29 GND 3 HD74ALVC16834 Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 *1, 2 Symbol VCC VI VO I IK I OK IO I CC or IGND PT Tstg Ratings –0.5 to 4.6 –0.5 to 4.6 –0.5 to VCC+0.5 –50 ±50 ±50 ±100 1 –65 to 150 Unit V V V mA mA mA mA W °C Conditions Output voltage range Input clamp current Output clamp current VI < 0 VO < 0 or VO > VCC VO = 0 to VCC Continuous output current VCC, GND current / pin Maximum power dissipation at Ta = 55°C (in still air) *3 Storage temperature range TSSOP Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating condition” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. The input and output positive-voltage ratings may be exceeded up to 4.6 V if the input and output clamp-current ratings are observed. 3. The maximum power dissipation is calculated using a junction temperature of 150°C and board trace length of 750 mils. Recommended Operating Conditions Item Supply voltage Input voltage Output voltage High-level output current Symbol VCC VI VO I OH Min 2.3 0 0 — — — Low-level output current I OL — — — Input transition rise or fall rate Operating free-air temperature ∆t/∆v Ta 0 –40 Max 3.6 VCC VCC –12 –12 –24 12 12 24 10 85 ns/V °C mA Unit V V V mA VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V Conditions Note: Unused or floating control pins must be held high or low. 4 HD74ALVC16834 Logic Diagram OE CLK LE A1 27 30 28 54 1D C1 CLK 3 Y1 To seventeen other channels 5 HD74ALVC16834 Electrical Characteristics Ta = –40 to 85°C Item Input voltage Symbol VCC (V) VIH 2.3 to 2.7 2.7 to 3.6 VIL 2.3 to 2.7 2.7 to 3.6 Output voltage VOH 2.3 to 3.6 2.3 2.3 2.7 3.0 3.0 VOL 2.3 to 3.6 2.3 2.3 2.7 3.0 Input current Off state output current I IN I OZ ∆ I CC 3.6 3.6 3.6 3.0 to 3.6 Min 1.7 2.0 — — VCC–0.2 2.0 1.7 2.2 2.4 2.0 — — — — — — — — — Max — — 0.7 0.8 — — — — — — 0.2 0.4 0.7 0.4 0.55 ±5.0 ±10 40 750 µA µA µA µA V V I OH = –100 µA I OH = –6 mA, VIH = 1.7 V I OH = –12 mA, VIH = 1.7 V I OH = –12 mA, VIH = 2.0 V I OH = –12 mA, VIH = 2.0 V I OH = –24 mA, VIH = 2.0 V I OL = 100 µA I OL = 6 mA, VIL = 0.7 V I OL = 12 mA, VIL = 0.7 V I OL = 12 mA, VIL = 0.8 V I OL = 24 mA, VIL = 0.8 V VIN = VCC or GND VOUT = VCC or GND VIN = VCC or GND One input at (V CC–0.6)V, other inputs at V CC or GND V Unit Test Conditions V Quiescent supply current I CC 6 HD74ALVC16834 Switching Characteristics (Ta = –40 to 85°C) Item Maximum clock frequency Symbol VCC (V) f max 2.5±0.2 2.7 3.3±0.3 Propagation delay time t PLH t PHL 2.5±0.2 2.7 3.3±0.3 2.5±0.2 2.7 3.3±0.3 2.5±0.2 2.7 3.3±0.3 Output enable time t ZH t ZL 2.5±0.2 2.7 3.3±0.3 Output disable time t .


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