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SH6511B Dataheets PDF



Part Number SH6511B
Manufacturers Sino Wealth
Logo Sino Wealth
Description 16K 4-Bit Microcontroller
Datasheet SH6511B DatasheetSH6511B Datasheet (PDF)

SH6511/SH6511B 16K 4-Bit Microcontroller with LCD Driver Features „ SH6610-based s ingle-chip 4-bi t M icrocontroller with LCD driver „ ROM: 16 K × 16 bits (bank switched) „ RAM: 512 × 4 bit s (system co ntrol register & data memory) „ Operating Voltage Range: 2.4V - 5.5V „ 8 CMOS I/O ports „ 4 level subroutine nesting including interrupts` „ One 8-bit timer with pre-divider circuit „ Warm-up timer for power-on reset „ Pow erful interrupt sources: -Timer0 interrupt -Port B interrupt (falling edg.

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SH6511/SH6511B 16K 4-Bit Microcontroller with LCD Driver Features „ SH6610-based s ingle-chip 4-bi t M icrocontroller with LCD driver „ ROM: 16 K × 16 bits (bank switched) „ RAM: 512 × 4 bit s (system co ntrol register & data memory) „ Operating Voltage Range: 2.4V - 5.5V „ 8 CMOS I/O ports „ 4 level subroutine nesting including interrupts` „ One 8-bit timer with pre-divider circuit „ Warm-up timer for power-on reset „ Pow erful interrupt sources: -Timer0 interrupt -Port B interrupt (falling edge) „ System clock: 2 M Hz single-p in v oltage-controlled oscillator „ Table Bran ch a nd Return C onstant I nstructions for Table Data Generation „ Data pointer with special system register control „ Two low power operating modes - HALT and STOP „ Instruction cycle tim e: 2 µs for 2 M Hz v oltagecontrolled oscillator „ Built-in 2-channel PSG for sound effects, switch able to noise channel „ D irectly drives speaker „ Type B LCD drive circuit „ LCD driver: 40 × 8 (1/8 duty cycle, 1/4 bias) „ LCD off by programming LCDOFF register „ Available in CHIP FORM General Description SH6511/SH6511B is a single chip 4 b it µC dedicated chip for handheld games. This device integrates a SH6610 4-bit CPU core with RAM, ROM, timer, 2-channel PSG, and dot matrix LCD driver. Pad Configuration S E G 2 0 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 S E G 3 9 46 S E G 4 0 45 T E S T 44 R E S E T 43 A O U T G N D 42 41 O P 0 V D D 39 40 38 37 O S C I O P 1 P A 0 36 35 P A 1 P A 2 34 P A 3 33 P B 0 2 S E G 1 9 3 S E G 1 8 4 S E G 1 7 5 S E G 1 6 6 S E G 1 5 7 S E G 1 4 8 S E G 1 3 9 S E S 1 2 10 S E G 1 1 S E G 1 0 S E G 9 13 S E G 8 14 15 16 17 18 19 20 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 PB3 PB2 PB1 11 12 SH6511/ SH6511B 21 22 23 24 25 26 27 28 29 30 31 32 1/22 Ver 2.2 http://www.Datasheet4U.com SH6511/SH6511B Block Diagram Segment Driver SEG1 - 40 LCD RAM RAM 2-Channel PSG TIMER0 MISC. CKT. RESET TEST OSCI AOUT CPU LCD Voltage 16K X 16 ROM PORTA COM1 - 8 Common Driver I/O Port PORTB Pad Description Pad No. 1 - 21, 46 - 64 22 - 29 30 - 33 34 - 37 38, 41 39 40 42 43 44 45 Symbol SEG1 - 40 COM8 -1 PB3 - PB0 PA3 - PA0 OP1, OP0 VDD OSCI GND AOUT RESET TEST O I I I I/O O O I/O O I PORT INT. 0FH 0 Shared by Reset Description Segment signal output for LCD display Common signal output for LCD display Bit programmable I/O, Vector Interrupt Output ports Bonding option Power supply OSC input Ground Audio output Reset input (active low) TEST ( No connect for user) 2/22 Ver 2.2 SH6511/SH6511B Functional Description 1. CPU The C PU core c ontains the fo llowing f unction blocks: Program C ounter, ALU, C arry Flag, Ac cumulator, Table Branch Register (TBR), Data Pointer (INX, DPH, DPM and DPL), and Stack. (a) PC (Program Counter) The PC is used for ROM addressing consisting of 12-bits: Page Register (PC11), and Ripple Carry Counter (PC10 - PC0). The program counter normally increases by one (+1) with each ex ecution of an i nstruction ex cept in t he f ollowing cases: 1) When executing a jump instruction (such as JMP, BA0, BAC); 2) When executing a subroutine call instruction (CALL); 3) When an interrupt occurs; 4) When t he c hip i s at INIT IAL RESET . T he program counter is l oaded w ith data c orresponding to ea ch instruction. The un conditional jump ins truction (JM P) can be set at 1-bit page register for higher than 2K. Program Counter can only address a 4K program ROM. To address 16K program ROM, use bank switch (Refer to the ROM description in Section 3 for details). (b) ALU and CY ALU performs arithmetic and logic operations. The ALU provides the following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjustment for addi tion/subtraction (D AA, D AS) Logic op erations (AN D, EO R, OR, AN DI, EO RI, ORI) Decision (BA0, BA1, BA2, BA3, BAZ, BAC) The C arry Flag (C Y) hold s th e ari thmetic op eration ALU overflow. During interr upt or c all instruction, c arry is pus hed onto stack and restored from stack by RTNI. It is unaffected by an RTNW instruction. (c) Accumulator Accumulator is a 4-bit re gister holding the r esults of the arithmetic logic unit. In conjunction with ALU, data transfers between the accumulator and system register, LCD RAM, or data memory can be performed. (d) Stack A group of registers used to save the contents of CY & PC (10-0) sequentially with each subroutine call or interrupt. It is organized 13 bits × 4 levels. The MSB is saved for CY. 4 levels are t he maximum allowed for s ubroutine c alls an d interrupts. The contents of Stack are returned sequentially to the PC with the retur n i nstructions (RT NI/RTNW). St ack i s operated on a f irst-in, last-out basis. T his 4-level nesting includes both subroutine calls and interrupt requests. Note that program execution may enter an abnormal state if the number of ca.


SH6511 SH6511B NT6611


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