DatasheetsPDF.com

SSM3J334R Dataheets PDF



Part Number SSM3J334R
Manufacturers Toshiba Semiconductor
Logo Toshiba Semiconductor
Description Silicon P-Channel MOSFET
Datasheet SSM3J334R DatasheetSSM3J334R Datasheet (PDF)

SSM3J334R TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSVI) SSM3J334R ○Power Management Switch Applications Unit: mm • Low ON-resistance: RDS(ON) = 71 mΩ (max) (@VGS = -10 V) RDS(ON) = 105 mΩ (max) (@VGS = -4.5 V) RDS(ON) = 136 mΩ (max) (@VGS = -4.0 V) Absolute Maximum Ratings (Ta = 25°C) Characteristic Symbol Rating Unit Drain-Source voltage VDSS -30 V Gate-Source voltage VGSS ± 20 V Drain current DC ID (Note 1) -4 A Pulse IDP (Note 1,2) -16 Power dis.

  SSM3J334R   SSM3J334R


Document
SSM3J334R TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSVI) SSM3J334R ○Power Management Switch Applications Unit: mm • Low ON-resistance: RDS(ON) = 71 mΩ (max) (@VGS = -10 V) RDS(ON) = 105 mΩ (max) (@VGS = -4.5 V) RDS(ON) = 136 mΩ (max) (@VGS = -4.0 V) Absolute Maximum Ratings (Ta = 25°C) Characteristic Symbol Rating Unit Drain-Source voltage VDSS -30 V Gate-Source voltage VGSS ± 20 V Drain current DC ID (Note 1) -4 A Pulse IDP (Note 1,2) -16 Power dissipation PD (Note 3) 1 W t < 10s 2 Channel temperature Storage temperature range Tch 150 °C Tstg −55 to 150 °C Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: The channel temperature should not exceed 150°C during use. Note 2: PW ≤ 1ms, Duty ≤ 1% Note 3: Mounted on a FR4 board. (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2) SOT-23F 1: Gate 2: Source 3: Drain JEDEC ― JEITA ― TOSHIBA 2-3Z1S Weight: 11 mg (typ.) Marking 3 KFL Equivalent Circuit (Top View) 3 1 2 1 2 © 2010 - 2018 1 Toshiba Electronic Devices & Storage Corporation Start of commercial production 2010-08 2018-10-04 SSM3J334R Electrical Characteristics (Ta = 25°C) Characteristic Symbol Test Conditions Min Typ. Max Unit Drain-Source breakdown voltage Drain cut-off current Gate leakage current Gate threshold voltage Forward transfer admittance Drain–source ON-resistance Input capacitance Output capacitance Reverse transfer capacitance Switching time Turn-on time Turn-off time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source forward voltage V (BR) DSS ID = -10 mA, VGS = 0 V -30   V V (BR) DSX ID = -10 mA, VGS = 10 V .(Note 5) -21   V IDSS VDS = -30 V, VGS = 0 V   -1 µA IGSS VGS = ±16 V, VDS = 0 V   ±10 µA Vth VDS = -10 V, ID = -100 µA -0.8  -2.0 V Yfs VDS = -10 V, ID = -1.0 A (Note 4) 2.3 4.6  S ID = -3.0 A, VGS = -10 V (Note 4)  54 71 RDS (ON) ID = -2.0 A, VGS = -4.5 V (Note 4)  80 105 mΩ ID = -1.0 A, VGS = -4.0 V (Note 4)  89 136 Ciss Coss Crss VDS = -15 V, VGS = 0 V f = 1 MHz  280   55  pF  40  ton VDD = -15 V, ID = -1.0 A toff VGS = 0 to -4.5 V, RG = 10 Ω  13  ns  22  Qg Qgs1 Qgd VDD = -15 V, ID = -4.0 A, VGS = -10 V  5.9   0.8  nC  1.2  VDSF ID = 4.0 A, VGS = 0 V (Note 4)  0.9 1.2 V Note4: Pulse test Note5: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drain-source breakdown voltage is lowered in this mode. Switching Time Test Circuit (a) Test Circuit 0 IN −4.5V 10 µs VDD = -15 V RG = 10 Ω Duty ≤ 1% VIN: tr, tf < 5 ns Common Source Ta = 25°C RG OUT RL VDD (b) VIN 0V −4.5 V (c) VOUT VDS (ON) VDD 90% 10% 90% 10% tr tf ton toff Notice on Usage Let Vth be the voltage applied between gate and source that causes the drain current (ID) to be low (-100μA for the SSM3J334R). Then, for normal switching operation, VGS(on) must be higher than Vth, and VGS(off) must be lower than Vth. This relationship can be expressed as: VGS(off) < Vth < VGS(on). Take this into consideration when using the device. Handling Precaution When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that come into direct contact with devices should be made of antistatic materials. Thermal resistance Rth (ch-a) and power dissipation PD vary depending on board material, board area, board thickness and pad area. When using this device, please take heat dissipation into consideration © 2010 - 2018 2 Toshiba Electronic Devices & Storage Corporation 2018-10-04 Drain current ID (A) ID – VDS -10 -10 V -4.5 V VGS = -4.0 V -8 -6 -4 -2 Common Source Ta = 25 °C Pulse test 0 0 -0.5 -1.0 -1.5 -2.0 Drain–source voltage VDS (V) Drain current ID (A) SSM3J334R -100 -10 Common Source VDS = -10 V Pulse test ID – VGS -1 -0.1 -0.01 -0.001 -0.0001 0 Ta = 100 °C −25 °C 25 °C -1.0 -2.0 -3.0 -4.0 Gate–source voltage VGS (V) RDS (ON) – VGS 200 ID = -1.0 A Common Source Pulse test 150 100 Ta = 100 °C 25 °C 50 − 25 °C 0 0 -4 -8 -12 -16 -20 Gate–source voltage VGS (V).


Si7856ADP SSM3J334R STB24NM60N


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)