Document
Data Sheet
16-Bit, 310 MSPS, 3.3 V/1.8 V Dual Analog-to-Digital Converter (ADC)
AD9652
FEATURES
High dynamic range SNR = 75.0 dBFS at 70 MHz (AIN = −1 dBFS) SFDR = 87 dBc at 70 MHz (AIN = −1 dBFS) Noise spectral density (NSD) = −156.7 dBFS/Hz input noise at −1 dBFS at 70 MHz NSD = −157.6 dBFS/Hz for small signal at −7 dBFS at 70 MHz 90 dB channel isolation/crosstalk On-chip dithering (improves small signal linearity)
Excellent IF sampling performance SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS) SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS) Full power bandwidth of 465 MHz
On-chip 3.3 V buffer Programmable input span of 2 V p-p to 2.5 V p-p (default)
Differential clock input receiver with 1, 2, 4, and 8 integer inputs (clock divider input accepts up to 1.24 GHz)
Internal ADC clock duty cycle stabilizer SYNC input allows multichip synchronization Total power consumption: 2.16 W
3.3 V and 1.8 V supply voltages DDR LVDS (ANSI-644 levels) outputs Serial port control Energy saving power-down modes
APPLICATIONS
Military radar and communications Multimode digital receivers (3G or 4G) Test and instrumentation Smart antenna systems
GENERAL DESCRIPTION
The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise floor of −157.6 dBFS and large signal spurious-free dynamic range (SFDR) performance (exceeding 85 dBFS, typical) allows low level signals to be resolved in the presence of large signals.
The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. A high performance on-chip buffer and internal voltage reference simplify the interface to external driving circuitry while preserving the exceptional performance of the ADC.
The AD9652 can support input clock frequencies of up to 1.24 GHz with a 1, 2, 4, and 8 integer clock divider to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle.
Rev. C
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FUNCTIONAL BLOCK DIAGRAM
AVDD3 AVDD SDIO SCLK CSB
DRVDD
VIN+A VIN–A
VREF SENSE
VCM RBIAS VIN–B VIN+B
AD9652
SPI
ADC
PROGRAMMING DATA
DDR DATA INTERLEAVER LVDS OUTPUT
DRIVER
16
REF SELECT
DIVIDE 1 TO 8
DUTY CYCLE
DCO
STABILIZER GENERATION
ADC
MULTICHIP SYNC
OR+, OR– D15± (MSB) TO D0± (LSB)*
CLK+ CLK– DCO+ DCO–
A.