ADSP-21060C

SHARC Processor ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC SUMMARY High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip Integrated multiprocessing features 240-lead thermally enhanced MQFP_PQ4 package, 225-ball plastic ball grid array (PBGA), 240-lead hermetic CQFP package RoHS compliant packages KEY FEATURES—PROCESSOR CORE 40 MIPS, 25 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Dual data address generators with modulo and bit-reverse addressing) Efficient program sequencing with zero-overhead looping: Single-cycle loop setup IEEE JTAG Standard 1149.1 Test Access Port and on-chip emulation 32-bit single-precision and 40-bit extended-precision IEEE floating-point data formats or 32-bit fixed-point data format CORE PROCESSOR INSTRUCTION CACHE 32  48-BIT DUAL-PORTED SRAM B LOCK 0 TWO INDEPENDENT DUAL-PORTED BLOCKS JTAG BLOCK 1 TEST AND EMULATION 7 TIMER DAG1 8  4  32 DAG2 8  4  24 PROCESSOR PORT I/O PORT ADDR DATA ADDR DATA DATA ADDR ADDR DATA PROGRAM SEQUENCER 24 32 IOD 48 IOA 17 EXTERNAL PORT 32 PM ADDRESS BUS DM ADDRESS BUS ADDR BUS MUX MULTIPROCESSOR INTERFACE PM DATA BUS BUS ...