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H5TQ1G83DFR-xxJ Dataheets PDF



Part Number H5TQ1G83DFR-xxJ
Manufacturers Hynix
Logo Hynix
Description 1Gb DDR3 SDRAM
Datasheet H5TQ1G83DFR-xxJ DatasheetH5TQ1G83DFR-xxJ Datasheet (PDF)

1Gb DDR3 SDRAM 1Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ1G83DFR-xxC H5TQ1G83DFR-xxI H5TQ1G83DFR-xxL H5TQ1G83DFR-xxJ H5TQ1G63DFR-xxC H5TQ1G63DFR-xxI H5TQ1G63DFR-xxL H5TQ1G63DFR-xxJ *Hynix Semiconductor reserves the right to change products or specifications without notice Rev. 1.7 /Sep. 2011 1 Free Datasheet http://www.Datasheet4U.com Revision History Revision No. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Added IDD Value Corrected Typo Error Corrected Typo Error(Ordering Information).

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1Gb DDR3 SDRAM 1Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ1G83DFR-xxC H5TQ1G83DFR-xxI H5TQ1G83DFR-xxL H5TQ1G83DFR-xxJ H5TQ1G63DFR-xxC H5TQ1G63DFR-xxI H5TQ1G63DFR-xxL H5TQ1G63DFR-xxJ *Hynix Semiconductor reserves the right to change products or specifications without notice Rev. 1.7 /Sep. 2011 1 Free Datasheet http://www.Datasheet4U.com Revision History Revision No. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Added IDD Value Corrected Typo Error Corrected Typo Error(Ordering Information) Added 1866/2133 Speed Support Added IDD Specification(1866/2133 Speed) Modified OPERATING FREQUENCY Table Added J and L-part support Updated 1866/2133 x8 IDD Specification and 1866 Frequency downbinning History Date Aug. 2010 Sep. 2010 Oct. 2010 Dec. 2010 Dec. 2010 Dec. 2010 Jun. 2011 Sep. 2011 Remark Rev. 1.7 /Sep. 2011 2 Free Datasheet http://www.Datasheet4U.com Description The H5TQ1G6(8)3DFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • DQ Power & Power supply : VDD & VDDQ = 1.5V +/0.075V • DQ Ground supply : VSSQ = Ground • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • Programmable BL=4 supported (tCCD=2CLK) for Digital consumer Applications. • Programmable ZQ calibration supported • BL switch on the fly • 8banks • On chip DLL align DQ, DQS and DQS transition with CK  • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) transition - 7.8 µs at -40oC ~ 85 oC • DM masks write data-in at the both rising and falling  - 3.9 µs at 85oC ~ 95 oC edges of the data strobe o o • All addresses and control inputs except data,  data strobes and data masks latched on the  rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported • Programmable additive latency 0, CL-1, and CL-2  supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10 • Programmable burst length 4/8 with both nibble sequential and interleave mode • Programmable PASR(Partial Array Self-Refresh) for Digital consumer Applications.  Commercial Temperature ( 0 C ~ 85 C) Industrial Temperature ( -40oC ~ 85 oC) • Auto Self Refresh supported • JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • On Die Thermal Sensor s.


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