HEF4526B

HEF4526B Programmable 4-bit binary down counter Rev. 5 — 22 November 2011 Product data sheet 1. General description The HEF4526B is a synchronous programmable 4-bit binary down counter with active HIGH and active LOW clock inputs (CP0, CP1), an asynchronous parallel load input (PL), four parallel inputs (A0 to A3), a cascade feedback input (CF), four buffered parallel outputs (Q0 to Q3), a terminal count output (TC), an overriding asynchronous master reset input (MR) and a decoded TC output that can be used for divide-by-n applications. In single stage applications the TC output is connected to PL. CF allows cascade divide-by-n operation with no additional gates required. Information on A0 to A3 is loaded into the counter while PL is HIGH, independent of all other inputs except MR, which must be LOW. When PL and CP1 are LOW, the counter advances on a LOW-to-HIGH transition of CP0. When PL is LOW and CP0 is HIGH, the counter advances on a HIGH to LOW transition of CP1. TC is HIGH when the counter is in the zero state (Q0 = Q1 = Q2 = Q3 = LOW) and CF is HIGH and PL is LOW. A HIGH on MR resets the counter (Q0 to Q3 = LOW) independent of other inputs. The clock input is highly tolerant of slower clock rise and fall times due to Schmitt trigger action. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits  Fully static operation  5 V, 10 V...