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HEF4042B Dataheets PDF



Part Number HEF4042B
Manufacturers NXP
Logo NXP
Description Quadruple D-latch
Datasheet HEF4042B DatasheetHEF4042B Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4042B MSI Quadruple D-latch Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple D-latch DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), fo.

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4042B MSI Quadruple D-latch Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple D-latch DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the same state, either HIGH or LOW. O0 to O3 follow D0 to D3 as long as both E0 and E1 remain in the same state. When E0 and E1 are different, D0 to D3 do not affect O0 to O3 and the information in the latch is stored. O0 to O3 are always the complement of O0 to O3. The exclusive-OR input structure allows the choice of either polarity for E0 and E1. With one enable input HIGH, the other enable input is active HIGH; with one enable input LOW, the other enable input is active LOW. HEF4042B MSI Fig.2 Pinning diagram. HEF4042BP(N): HEF4042BD(F): HEF4042BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING D0 to D3 E0 and E1 O0 to O3 O0 to O3 data inputs enable inputs parallel latch outputs complementary parallel latch outputs APPLICATION INFORMATION Some examples of applications for the HEF4042B are: • Buffer storage • Holding register FAMILY DATA, IDD LIMITS category MSI See Family Specifications Fig.1 Functional diagram. January 1995 2 Philips Semiconductors Product specification Quadruple D-latch FUNCTION TABLE E0 L L H H Note E1 L H L H HEF4042B MSI OUTPUT On Dn latched latched Dn 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage). Fig.3 Logic diagram. Fig.4 Logic diagram (one latch). January 1995 3 Philips Semiconductors Product specification Quadruple D-latch AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays D → O, O HIGH to LOW 5 10 15 5 LOW to HIGH E → O, O HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH Set-up time D→E Hold time D→E Minimum enable pulse width 10 15 5 10 15 5 10 15 5 10 15 tWE thold tsu 30 20 20 15 15 15 90 40 30 tTLH tTHL 60 30 20 60 30 20 10 5 5 −5 0 0 45 20 15 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 15 tPLH tPHL tPLH tPHL 95 40 30 85 40 30 130 50 35 120 50 35 190 80 55 175 75 60 260 105 75 245 105 75 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX. HEF4042B MSI TYPICAL EXTRAPOLATION FORMULA 67 ns + (0,55 ns/pF) CL 28 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 57 ns + (0,55 ns/pF) CL 28 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 102 ns + (0,55 ns/pF) CL 38 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 92 ns + (0,55 ns/pF) CL 38 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL see also waveforms Figs 5 and 6 VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 3800 fi + ∑ (foCL) × VDD2 15 700 fi + ∑ (foCL) × 41 100 fi + ∑ (foCL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification Quadruple D-latch HEF4042B MSI Either E0 or E1 is held HIGH or LOW while the other enable input is pulsed as the function table shows. Fig.5 Waveforms showing propagation delays for D to O, with latch enabled. January 1995 5 Philips Semiconductors Product specification Quadruple D-latch HEF4042B MSI Fig.6 Waveforms showing minimum enable pulse width, set-up time and hold time for E and D. Set-up and hold-times are shown as positive values but may be specified as negative values. January 1995 6 .


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