Document
MST705 Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0.1
FEATURES
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Video Decoder Ÿ Supports NTSC, PAL and SECAM video input formats Ÿ 2D NTSC and PAL comb-filter for Y/C separation of CVBS input Ÿ Multiple CVBS and S-video inputs Ÿ ACC, AGC, and DCGC (Digital Chroma Gain Control) Analog Input Ÿ Supports RGB input format from PC, camcorders and GPS Ÿ Supports YCbCr inputs from conventional video source and HDTV Ÿ Supports video input 480i, 480p, 576i, 576p, 720p, 1080i; 1080P; RGB input resolution in 640x480, 800x480, and 800x600, 1024x768, 1280x1024 Ÿ 3-channel low-power 10-bit ADCs integration for YCbCr and RGB Ÿ Supports RGB composite sync input (CSYNC), SOY, SOG, HSYNC, and VSYNC Ÿ On-chip clock synthesizer and PLL Ÿ Auto-position adjustment, auto-phase adjustment, auto-gain adjustment, and auto-mode detection
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Color Engine Ÿ Brightness, contrast, saturation, and hue adjustment Ÿ 9-tap programmable multi-purpose FIR (Finite Impulse Response) filter Ÿ Differential 3-band peaking engine Ÿ Luminance Transient Improvement (LTI) Ÿ Chrominance Transient Improvement (CTI) Ÿ Black Level Extension (BLE) Ÿ White Level Extension (WLE) Ÿ Favor Color Compensation (FCC) Ÿ 3-channel gamma curve adjustment Scaling Engine/Panel Interface Ÿ Supports LVDS panel up to 1366x768 Ÿ Supports TTL/TCON and analog TCON panel Ÿ Supports single 8-bit TTL panel output Ÿ Supports various displaying modes Ÿ Supports horizontal panorama scaling Miscellaneous Ÿ Built-in MCU Ÿ Supports CCIR656 digital input Ÿ Built-in internal OSD with 256 programmable fonts, 16-color palettes, and 12-bit color resolution Ÿ Spread spectrum clocks Ÿ 3.3V output pads with programmable driving current Ÿ 100-pin LQFP package
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-1Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.
11/2/2010
Free Datasheet http://www.datasheet4u.net/
MST705 Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0.1
BLOCK DIAGRAM
R/Cr RGB /YCbCr G/Y B/Cb CVBS 1/2 Switch SY/CVBS S-Video 1/2 SC Auto Function for RGB / YCbCr ADC Input
2-Channel AFE
Video Decoder Timing Generator
YC Separation 2D Comb Filter
Chroma Demodulator
M U X
3x3 Color Space Conversion
MACE
Scaling Engine
CSC (RGB to YCbCr)
OSD
Gamma
Display Unit
T-CON
Display Device
SYSTEM APPLICATION DIAGRAM
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Flash Memory or EEPROM External MCU
MCU
BIU
Flash / ROM
1.8V
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MicroController
PWM Step-Down
TV / Cable Signal
TV Tuner Video Decoder
Additional CVBS DVD / VCD S-Video Signal Additional S-Video Additional RGB Signal HDTV YPbPr Signal
TCON
To Digital Panel
Deinterlacer / Scaler
TTL
TTL Out
-2Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.
11/2/2010
Free Datasheet http://www.datasheet4u
MST705 Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0.1
GENERAL DESCRIPTION
The MST705 is a high quality ASIC for NTSC/PAL/SECAM car TV application. It receives analog NTSC/PAL/SECAM CVBS and S-Video inputs from TV tuners, DVD or VCR sources, including weak and distorted signals, as well as analog YCbCr input from HDTV/SDTV systems. Automatic gain control (AGC) and 10-bit 3-channel A/D converters provide high resolution video quantization. With automatic video source and mode detection, users can easily switch and adjust variety of signal sources. Multiple internal adaptive PLLs precisely extract pixel clock from video source and perform sharp color demodulation. Built-in line-buffer supports adaptive 2-D comb-filter, 2-D sharpening, and synchronization stabler in a condense manner. The output format of MST705 supports 6-bit TTL/TCON and LVDS digital TFT-LCD modules.
Mstar Confidential for mñ W3^ l_T/yÑb€g Internal Use Only
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-3Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.
11/2/2010
Free Datasheet http://www.datasheet4u.net/
MST705 Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0.1
PIN DIAGRAM (MST705)
AVDD_MPLL XTAL_IN XTAL_OUT AGND GPIO[25]/PWM4D GPIO[24]/PWM3D GPIOE GPIOD TCON[1] GND BOUT[7]/TCON[2] BOUT[6]/TCON[3] BOUT[5] BOUT[4] BOUT[3] BOUT[2]
100 99 98 97 95 94 93 92 91 90 89 88 87 86 85
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83
82
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79
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77
AVDD_ANA BIN0/PBIN0 SOG0 GIN0/YIN0 RGBINM0 RIN0/PRIN0 HSYNCIN VSYNCIN AGND BIN1/PBIN1 RGBINM1 GIN1/YIN1 SOG1 RIN1/PRIN1 VCOM0 CVBS1/SC0 CVBS2/SY0 CVBS3/SC1 CVBS4/SY1 GND DPWM_IFB DPWM_QOR VDDP CP_N CP_P
76
96
BOUT[1] BOUT[0] AVDD_DAC VCOMOUT VREP_DAC DAC_VB GND DAC_VG DAC_VR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74
Pin 1
73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
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CLKIN VD[0] VD[1] VD[2] VD[3] VD[4] VD[5] VD[6] VD[7] VDDC GND GND SAR0 SAR1 SAR2 SCK SDI SDO CSN GPIOA INT TXD_SDA RXD_.