Document
TC4013BP/BF/BFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC4013BP,TC4013BF,TC4013BFN
TC4013B Dual D-Type Flip Flop
TC4013B contains two independent circuits of D type flip-flop. The input level applied to DATA input are transferred to Q and Q output by rising edge of the clock pulse. When SET input is placed at “H”, and RESET input is placed at “L”, outputs become Q = “H”, and Q = “L”. When RESET input is placed at “H”, and SET input is placed at “L”, outputs become Q = “L”, and Q = “H”. When both of RESET input and SET input are at “H”, outputs become Q = “H” and Q = “H”.
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in Japan.
TC4013BP
TC4013BF
Block Diagram
TC4013BFN
Weight DIP14-P-300-2.54 SOP14-P-300-1.27A SOL14-P-150-1.27
: 0.96 g (typ.) : 0.18 g (typ.) : 0.12 g (typ.)
1 2007-10-01
Truth Table
RESET L H H L L L
Inputs SET DATA
H* L* H* LL LH L*
*: Don’t care Δ: Level change ・: No change
CKΔ * * *
Logic Diagram
Outputs Qn + 1 Qn + 1
HL LH HH LH HL Qn・ Qn ・
TC4013BP/BF/BFN
Absolute Maximum Ratings (Note)
Characteristics
Symbol
Rating
Unit
DC supply voltage Input voltage Output voltage DC input current Power dissipation Operating temperature range Storage temperature range
VDD VIN VOUT IIN PD Topr Tstg
VSS − 0.5~VSS + 20 VSS − 0.5~VDD + 0.5 VSS − 0.5~VDD + 0.5
±10 300 (DIP)/180 (SOIC)
−40~85 −65~150
V V V mA mW °C °C
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc).
2 2007-10-01
TC4013BP/BF/BFN
Operating Ranges (VSS = 0 V) (Note)
Characteristics
Symbol
Test Condition
Min Typ. Max Unit
DC supply voltage Input voltage
VDD VIN
⎯ 3 ⎯ 18 V ⎯ 0 ⎯ VDD V
Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VDD or VSS.
Static Electrical Characteristics (VSS = 0 V)
Characteristics
High-level output voltage
Low-level output voltage
Output high current
Output low current
Input high voltage
Input low voltage
Input current
“H” level “L” level
Quiescent supply current
Symbol VOH VOL
IOH
IOL
VIH
VIL IIH IIL IDD
Test Condition
VDD (V)
⎪IOUT⎪ < 1 μA VIN = VSS, VDD
5 10 15
⎪IOUT⎪ < 1 μA VIN = VSS, VDD
5 10 15
VOH = 4.6 V VOH = 2.5 V VOH = 9.5 V VOH = 13.5 V VIN = VSS, VDD VOL = 0.4 V VOL = 0.5 V VOL = 1.5 V VIN = VSS, VDD VOUT = 0.5 V, 4.5 V VOUT = 1.0 V, 9.0 V VOUT = 1.5 V, 13.5 V ⎪IOUT⎪ < 1 μA VOUT = 0.5 V, 4.5 V VOUT = 1.0 V, 9.0 V VOUT = 1.5 V, 13.5 V ⎪IOUT⎪ < 1 μA VIH = 18 V VIL = 0 V
VIN = VSS, VDD (Note)
5 5 10 15
5 10 15
5 10 15
5 10 15
18 18 5 10 15
−40°C
Min Max
4.95 9.95 14.95
⎯ ⎯ ⎯ −0.61 −2.50 −1.50 −4.00
⎯ ⎯ ⎯ 0.05 0.05 0.05 ⎯ ⎯ ⎯ ⎯
0.61 ⎯ 1.50 ⎯ 4.00 ⎯
3.5 ⎯ 7.0 ⎯ 11.0 ⎯
⎯ 1.5 ⎯ 3.0 ⎯ 4.0
⎯ 0.1 ⎯ −0.1 ⎯1 ⎯2 ⎯4
25°C
Min Typ.
4.95 9.95 14.95
⎯ ⎯ ⎯ −0.51 −2.10 −1.30 −3.40
5.00 10.00 15.00 0.00 0.00 0.00 −1.0 −4.0 −2.2 −9.0
0.51 1.2 1.30 3.2 3.40 12.0
3.5 2.75 7.0 5.50 11.0 8.25
⎯ 2.25 ⎯ 4.50 ⎯ 6.75
⎯ 10−5 ⎯ −10−5 ⎯ 0.002 ⎯ 0.004 ⎯ 0.008
Max ⎯ ⎯ ⎯ 0.05 0.05 0.05 ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯
⎯ ⎯ ⎯
1.5 3.0 4.0
0.1 −0.1
1 2 4
85°C
Min Max
4.95 9.95 14.95
⎯ ⎯ ⎯ −0.42 −1.70 −1.10 −2.80
⎯ ⎯ ⎯ 0.05 0.05 0.05 ⎯ ⎯ ⎯ ⎯
0.42 ⎯ 1.10 ⎯ 2.80 ⎯
3.50 7.00 11.00
⎯ ⎯ ⎯
⎯ 1.5 ⎯ 3.0 ⎯ 4.0
⎯ 1.0 ⎯ −1.0 ⎯ 30 ⎯ 60 ⎯ 120
Note: All valid input combinations.
Unit V V mA
mA V V μA μA
3 2007-10-01
TC4013BP/BF/BFN
Dynamic Electrical Characteristics (Ta = 25°C, VSS = 0 V, CL = 50 pF)
Characteristics
Output transition time (low to high)
Output transition time (high to low)
Propagation delay time (CK-Q, Q )
Propagation delay time (SET, RESET-Q, Q )
Propagation delay time (SET, RESET-Q, Q )
Max clock frequency
Max clock input rise time Max clock input fall time
Min pulse width (SET, RESET)
Min clock pulse width
Min set-up time (DATA-CK)
Min hold time (DATA-CK)
Min removal time (SET, RESET-CK) Input capacitance
Symbol tTLH
tTHL tpLH tpHL tpLH
tpHL
fCL trCL tfCL tW
tW
tsu
tH
trem CIN
Test Condition ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯
VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15
Min Typ. Max
⎯ 70 200
⎯ 35 100
⎯ 30 80
⎯ 70 200
⎯ 35 100
⎯ 30 80
⎯ 130 300
⎯ 65 130
⎯ 50 90
⎯ 110 300
⎯ 50 130
⎯ 40 90
⎯ 110 300
⎯ 50 130
⎯ 40 90
3.5 8 ⎯
8.0 16
⎯
12.0 20
⎯
No limit
⎯ 60 180 ⎯ 30 80 ⎯ 25 50 ⎯ 60 140 ⎯ 30 60 ⎯ 25 40 ⎯ ⎯ 40 ⎯ ⎯ 20 ⎯ .