Document
Datasheet
RX111 Group
Renesas MCUs
R01DS0190EJ0100 Rev.1.00 Jun 19, 2013
32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory, USB 2.0 full-speed host/function/OTG, up to 6 comms channels, 12-bit A/D, 8-bit D/A, RTC
Features
■ 32-bit RX CPU core 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle) Fast interrupt CISC Harvard architecture with five-stage pipeline Variable-length instruction format, ultra-compact code On-chip debugging circuit ■ Low power consumption functions Operation from a single 1.8 to 3.6 V supply Three low power consumption modes ■ On-chip flash memory for code, no wait states Operation at 32 MHz, read cycle of 31.25 ns No wait states for reading at full CPU speed 16 to 128 Kbyte capacities Programmable at 1.8 V For instructions and operands ■ On-chip data flash memory 8 Kbytes 1,000,000 Erase/Write cycles (typ.) BGO (Background Operation) ■ On-chip SRAM, no wait states 8 to 16 Kbyte capacities ■ Data transfer controller (DTC) Four transfer modes Transfer can be set for each interrupt source. ■ Event link controller (ELC) Module operation can be initiated by event signals without going through interrupts. Link operation between modules is possible while the CPU is sleeping. ■ Reset and power supply voltage management Six types including Power-On Reset (POR) Low voltage detection (LVD) with voltage settings ■ Clock functions External clock input frequency: Up to 20 MHz Main clock oscillator frequency: 1 to 20 MHz Sub-clock oscillator frequency: 32.768 kHz PLL circuit input: 4 to 8 MHz Low-speed on-chip oscillator: 4 MHz High-speed on-chip oscillator: 32 MHz IWDT-dedicated on-chip oscillator: 15 kHz Generate a dedicated 32.768-kHz clock for the RTC On-chip clock frequency accuracy measurement circuit (CAC) ■ Realtime clock (RTC) 30-second, leap year, and error adjustment functions Calendar count mode or binary count mode selectable Capable of initiating exit from software standby mode
PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch PLQP0064GA-A 14 × 14 mm, 0.8 mm pitch PLQP0048KB-A 7 × 7 mm, 0.5 mm pitch
PWQN0048KB-A 7 × 7 mm, 0.50 mm pitch PWQN0040KC-A 6 × 6 mm, 0.50 mm pitch
PWLG0064KA-A 5 × 5 mm, 0.5 mm pitch PWLG0036KA-A 4 × 4 mm, 0.5 mm pitch
■ Independent watchdog timer (IWDT) 15-kHz on-chip oscillator produces a dedicated clock signal to drive IWDT operation. ■ On-chip functions for IEC 60730 compliance Clock frequency accuracy measurement circuit, IWDT, functions to assist in RAM testing, etc. ■ Up to six channels for communication USB: USB 2.0 host (32 Kbyte or more ROM)/function/ On-The-Go (OTG) (one channel), full-speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and BC (Battery Charger) supported SCI: Asynchronous mode, clock synchronous mode, smart card interface (up to three channels) I2C bus interface: Transfer at up to 400 kbps, capable of SMBus operation (one channel) RSPI (one channel) ■ Up to 8 extended-function timers 16-bit MTU: Input capture/output compare, complementary PWM output, phase counting mode (six channels) 16-bit CMT (two channels) ■ 12-bit A/D converter Up to 14 channels 1.0 μs minimum conversion speed Double trigger (data duplication) function for motor control ■ 8-bit D/A converter Two channels (for 64 pins only) ■ Temperature sensor ■ General I/O ports 5-V tolerant, open drain, input pull-up ■ Multi-function pin controller (MPC) Multiple I/O pins can be selected for peripheral functions. ■ Operating temperature range 40 to 85C 40 to 105°C
R01DS0190EJ0100 Rev.1.00 Jun 19, 2013
Page 1 of 107
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RX111 Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different Packages.
Table 1.1
Classification CPU
Outline of Specifications (1/3)
Module/Function CPU Description Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit On-chip divider: 32-bit ÷ 32-bit → 32 bits Barrel shifter:.