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9250-08 Dataheets PDF



Part Number 9250-08
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description ICS9250-08
Datasheet 9250-08 Datasheet9250-08 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS9250-08 Frequency Generator & Integrated Buffers for Celeron & PII/III™ Recommended Application: BX, Appollo Pro 133 type of chip set. Output Features: • 3 - CPUs @2.5V, up to 150MHz. • 17 - SDRAM @ 3.3V, up to 150MHz. • 7 - PCI @3.3V • 2 - IOAPIC @ 2.5V • 1 - 48MHz, @3.3V fixed. • 1 - 24MHz @ 3.3V • 2 - REF @3.3V, 14.318MHz. Features: • Up to 150MHz frequency support • Support power management: CPU, PCI, stop and Power down Mode form I2C programming. • Spre.

  9250-08   9250-08


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Integrated Circuit Systems, Inc. ICS9250-08 Frequency Generator & Integrated Buffers for Celeron & PII/III™ Recommended Application: BX, Appollo Pro 133 type of chip set. Output Features: • 3 - CPUs @2.5V, up to 150MHz. • 17 - SDRAM @ 3.3V, up to 150MHz. • 7 - PCI @3.3V • 2 - IOAPIC @ 2.5V • 1 - 48MHz, @3.3V fixed. • 1 - 24MHz @ 3.3V • 2 - REF @3.3V, 14.318MHz. Features: • Up to 150MHz frequency support • Support power management: CPU, PCI, stop and Power down Mode form I2C programming. • Spread spectrum for EMI control (0 to -0.5%, ± 0.25%). • Uses external 14.318MHz crystal Key Specifications: • CPU – CPU: <175ps • CPU – PCI: min = 1ns max = 4ns • PCI – PCI: <250ps • SDRAM - SDRAM: <500ps Pin Configuration VDDREF *FS2/REF1 *PCI_STOP/REF0 GND X1 X2 VDDPCI *MODE/PCICLK_F **FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDPCI PCICLK5 BUFFERIN SDRAM11 SDRAM10 VDDSDR SDRAM9 SDRAM8 GND SDRAM15 SDRAM14 GND SDATA 2 I C SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDLIOAPIC IOAPIC0 IOAPIC_F GND CPUCLK_F CPUCLK1 VDDLCPU CPUCLK2 GND CPU_STOP# SDRAM_F VDDSDR SDRAM0 SDRAM1 GND SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 GND SDRAM12 SDRAM13 VDD48 24MHz/FS0* 48MHz/FS1* { 56-Pin SSOP Block Diagram PLL2 ÷2 * Internal Pull-up Resistor of 240K to 3.3V on indicated inputs ** Internal Pull-down resistor of 240K to GND on indicated inputs. 48MHz 24MHz IOAPIC_F Functionality FS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 FS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU (MHz) 133 124 150 140 105 110 115 120 100.3 133 112 103 66.8 83.3 75 124 PCICLK (MHz) 33.3 (CPU/4) 31 (CPU/4) 37.5 (CPU/4) 35 (CPU/4) 35 (CPU/3) 36.67 (CPU/3) 38.33 (CPU/3) 40.00 (CPU/3) 33.43 (CPU/3) 44.33 (CPU/3) 37.33 (CPU/3) 34.33 (CPU/2) 33.40 (CPU/2) 41.65 (CPU/2) 37.5 (CPU/2) 41.33 (CPU/2) X1 X2 XTAL OSC STOP IOAPIC0 2 REF [1:0] CPUCLK_F CPUCLK [2:1] PLL1 Spread Spectrum FS[3:0] MODE POR LATCH 1 STOP 2 4 PCI CLOCK DIVDER STOP 6 PCICLK [5:0] PCICLK_F CPU_STOP# PCI_STOP# 2 Control Logic Config. Reg. STOP I C SCLK { SDATA 16 SDRAM [15:0] SDRAM_F BUFFERIN 9250-08 Rev H 10/8/99 Third party brands and names are the property of their respective owners. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. Free Datasheet http://www.datasheet4u.com/ ICS9250-08 ICS9250-08 Pin Configuration PIN NUMBER 2 P I N NA M E REF1 FS21 REF0 P C I _ S TO P # 1 TYPE OUT IN OUT IN PWR IN OUT OUT IN IN OUT OUT IN IN IN OUT IN OUT IN PWR DESCRIPTION 14.318 MHz reference clock output L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D P C I 14.318MHz reference clock output Halts PCICLK [5:0] at logic "0" level when low. (in mobile, MODE=0) Ground. 14.318MHz input. Has internal load cap, (nominal 33pF). Crystal output. Has internal load cap (33pF) and feedback resistor to X1 Free running BUS clock not affected by PCI_STOP# Latched input for MODE select. Converts pin 3 to PCI_STOP# when low for power management. Latched frequency select input, pull-down Free running BUS clock not affected by PCI_STOP# PCI Clock Outputs. Input for Buffers S e r i a l d a t a i n f o r s e r i a l c o n fi g p o r t . ( I 2 C ) Clock input for serial config port. (I2C) 24MHz clock output for Super I/O or FD. L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D 4 . 48MHz clock output for USB. L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D 2 . Nominal 3.3V power supply, see power groups for function. 3 4, 10, 23, 26, 34, 42, GND 48, 53 5 6 8 X1 X2 PCICLK_F MODE1 FS31 PCICLK0 PCICLK [5:1] BU F F E R I N SDATA SCLK 24MHz 30 FS01 29 1, 7, 15, 20, 31, 37, 45 24, 25, 32, 33, 18, 19, 21, 22, 35, 36, 38, 39, 40, 41, 43, 44 46 47 50, 56 55 51, 49 52 54 48MHz FS11 VDDPCI, VDDREF, VDDSDR, VDD48 SDRAM [15:0] 9 16, 14, 13, 12, 11 17 27 28 OUT SDRAM clocks SDRAM_F C P U _ S TO P # VDDLCPU, VDDLIOAPIC I OA P I C 0 CPUCLK [2:1] CPUCLK_F I OA P I C _ F OUT IN PWR OUT OUT OUT OUT Free running SDRAM clock Not affected by CPU_STOP# Halts CPUCLK [2:1], IOAPIC0, SDRAM [15:0] clocks at logic "0" level when low. CPU and IOAPIC clock buffer power supply, 2.5V nominal. IOAPIC clock output. (14.318 MHz) Poweredby VDDLIOAPIC CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz) Free running CPU output clock. Not affected ty the CPU_STOP#. Freerunning IOAPIC clock output. Not affected by the CPU_STOP# (14.31818 MHz) Powered by VDDLIOAPIC Notes: 1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logi.


285D 9250-08 OB33


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