IC42S16800

IC42S81600/IC42S81600L IC42S16800/IC42S16800L Document Title 4(2)M x 8(16) Bit x 4 Banks (128-MBIT) SDRAM Revision History Revision No 0A 0B 0C 0D 0E History Initial Draft Corrected typo on PIN FUNCTIONS and revise DC OPERATING CONDITIONS Append two parameters tDPL ,tDAL;correct tRCD and tRP and modify DC operating condition 1.Obsolete speed grade -7H 2.Support Pb-free package 3.Modify typo in page 16,17 Add Industrial range Change ICC5 from 160mA to 180mA Draft Date August 27,2001 May 6,2002 August 21,2003 Remark September 09,2003 June 11,2004 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR023-0E 6/11/2004 1 IC42S81600/IC42S81600L IC42S16800/IC42S16800L 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES Single 3.3V (± 0.3V) power supply High speed clock cycle time -6: 166MHz<3-3-3>, -7H: 133MHz<2-2-2>, -7: 133MHz<3-3-3>, -8: 100MHz<2-2-2> Fully synchronous operation referenced to clock rising edge Possible to assert random column access in every cycle Quad internal banks contorlled by BA0 & BA1 (Bank Select) Byte control by LDQM and UDQM for IC42S16800 Programmable Wrap sequence (Sequential / Interleave) Programmable burst length (1, 2, 4, 8 and full page) Programmable CAS latency (2 and 3) A...