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X4643 Dataheets PDF



Part Number X4643
Manufacturers Xicor
Logo Xicor
Description (X4643 / X4645) CPU Supervisor
Datasheet X4643 DatasheetX4643 Datasheet (PDF)

Preliminary Information 64K X4643/5 CPU Supervisor with 64K EEPROM DESCRIPTION 8K x 8 Bit FEATURES • Selectable watchdog timer • Low VCC detection and reset assertion —Four standard reset threshold voltages —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog off —3mA active current • 64Kbits of EEPROM —64-byte page write mode —Self-timed write cycle —.

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Preliminary Information 64K X4643/5 CPU Supervisor with 64K EEPROM DESCRIPTION 8K x 8 Bit FEATURES • Selectable watchdog timer • Low VCC detection and reset assertion —Four standard reset threshold voltages —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog off —3mA active current • 64Kbits of EEPROM —64-byte page write mode —Self-timed write cycle —5ms write cycle time (typical) • Built-in inadvertent write protection —Power-up/power-down protection circuitry • 400kHz 2-wire interface • 2.7V to 5.5V power supply operation • Available packages —8-lead SOIC —8-lead TSSOP The X4643/5 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the set minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry BLOCK DIAGRAM Watchdog Transition Detector WP Data Register Command Decode & Control Logic VCC Threshold Reset Logic Block Lock Control Protect Logic Status Register EEPROM Array RESET (X4643/5) RESET (X4645) Watchdog Timer Reset SDA SCL S0 S1 Reset & Watchdog Timebase 8Kbit VCC VTRIP + - Power on and Low Voltage Reset Generation REV 1.26 4/30/02 www.xicor.com Characteristics subject to change without notice. 1 of 22 Free Datasheet http://www.datasheet4u.com/ X4643/5 – Preliminary Information standard VTRIP thresholds are available, however, Xicor’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to finetune the threshold for applications requiring higher precision. PIN CONFIGURATION 8-Pin JEDEC SOIC S0 S1 RESET/RESET VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8 Pin TSSOP WP VCC S0 S1 1 2 3 4 8 7 6 5 SCL SDA VSS RESET/RESET PIN FUNCTION Pin (SOIC) 1 2 3 Pin (TSSOP) 3 4 5 Name S0 S1 Device Select Input Device Select Input Function RESET/ RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms. RESET/ RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power up and remains active for 250ms after the power supply stabilizes. Ground Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. Serial Clock. The Serial Clock controls the serial bus timing for data input and output. Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control register. Supply Voltage 4 5 6 7 VSS SDA 6 7 8 8 1 2 SCL WP VCC REV 1.26 4/30/02 www.xicor.com Characteristics subject to change without notice. 2 of 22 Free Datasheet http://www.datasheet4u.com/ X4643/5 – Preliminary Information PRINCIPLES OF OPERATION Power On Reset Application of power to the X4643/5 activates a Power On Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to stabilization of the oscillator. – It allows time for an FPGA to download its configuration prior to initialization of the circuit. – It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power up. When VCC exceeds the device VTRIP threshold value for 200ms (nominal) the circuit releases RESET/ RESET allowing the system to begin operation. LOW VOLTAGE MON.


EZJS2YD472 X4643 X4645


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