Document
TC58NVG2S3ETA00
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4 GBIT (512M × 8 BIT) CMOS NAND E PROM DESCRIPTION
The TC58NVG2S3E is a single 3.3V 4 Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 4096blocks. The device has two 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages). The TC58NVG2S3E is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage.
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FEATURES
• Organization Memory cell array Register Page size Block size • x8 2112 × 256K × 8 2112 × 8 2112 bytes (128K + 4K) bytes
Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 4016 blocks Max 4096 blocks Power supply VCC = 2.7V to 3.6V Access time Cell array to register Serial Read Cycle Program/Erase time Auto Page Program Auto Block Erase Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby 30 µs max 25 ns min (CL=100pF) 300 µs/page typ. 2.5 ms/block typ. 30 mA max. 30 mA max 30 mA max 50 µA max
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Package TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
1
2012-09-01
Free Datasheet http://www.datasheet4u.com/
TC58NVG2S3ETA00
PIN ASSIGNMENT (TOP VIEW)
TC58NVG2S3ETA00
×8 ×8
NC NC NC NC NC NC
RY / BY
RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC
PINNAMES
I/O1 to I/O8 I/O port
CE
WE RE CLE ALE WP RY/BY VCC VSS
Chip enable
Write enable Read enable Command latch enable Address latch enable Write protect Ready/Busy Power supply Ground
2
2012-09-01
Free Datasheet http://www.datasheet4u.com/
TC58NVG2S3ETA00
BLOCK DIAGRAM
VCC VSS Status register
I/O1 to I/O8 I/O Control circuit
Address register
Column buffer Column decoder
Command register
Data register Sense amp
Row address decoder
CE CLE ALE WE RE WP Logic control Control circuit
Row address buffer decoder
Memory cell array
RY / BY RY / BY HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC VIN VI/O PD TSOLDER TSTG TOPR Power Supply Voltage Input Voltage Input /Output Voltage Power Dissipation Soldering Temperature (10 s) Storage Temperature .