H5TQ4G43MMR-xxC

H5TQ4G43MMR-xxC H5TQ4G83MMR-xxC 4Gb DDR3 SDRAM DDP(2Gbx2) H5TQ4G43MMR-xxC H5TQ4G83MMR-xxC Rev. 0.1 / Aug 2008 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. 1 Free Datasheet http://www.datasheet4u.com/ H5TQ4G43MMR-xxC H5TQ4G83MMR-xxC Revision History Revision No. 0.1 History Initial Release (Preliminary version) Draft Date 2008-8 Remark Rev. 0.1 /Aug 2008 2 Free Datasheet http://www.datasheet4u.com/ H5TQ4G43MMR-xxC H5TQ4G83MMR-xxC Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Description 1.1.2 Features 1.1.3 Ordering Information 1.1.4 Ordering Frequency 1.2 Package Ball out 1.3 Row and Column Address Table: 512M/1G Fixed 1.4 Pin Functional Description 1.5 Functional Block Diagram 2. Command Description 2.1 Command Truth Table 2.2 Clock Enable (CKE) Truth Table for Synchronous Transitions 3. Absolute Maximum Ratings 4. Operating Conditions 4.1 Operating Temperature Condition 4.2 DC Operating Conditions 5. AC and DC Input Measurement Levels 5.1 AC and DC Logic Input Levels for Single-Ended Signals 5.2 AC and DC Logic Input Levels for Differential Signals 5.3 Differential Input Cross Point Voltage 5.4 Slew Rate Definitions for Single Ended Input Signals 5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) 5.4.2 Input Slew Rate for Input Hold Time (tIH) ...