Document
S i 5 3 0 / 5 31
P R E L I M I N A R Y D A TA S H E E T
C R Y S TA L O S C I L L A T O R (XO) (10 M H Z T O 1.4 G H Z )
Features
Available with any-rate output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz 3rd generation DSPLL® with superior jitter performance 3x better frequency stability than SAW-based oscillators
Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant
Si5602
Ordering Information: See page 6.
Applications
SONET/SDH Networking SD/HD video
Clock and data recovery FPGA/ASIC clock generation
Pin Assignments: See page 5. (Top View)
NC OE GND 1 2 3 6 5 4 VDD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si530/531 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si530/531 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si530/531 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators.
CLK– CLK+
Si530 (LVDS/LVPECL/CML)
OE NC GND
1 2 3
6 5 4
VDD
Functional Block Diagram
V DD CLK– CLK+
NC CLK+
Si530 (CMOS)
Fixed Frequency XO
Any-rate 10–1400 MHz DSPLL® Clock Synthesis
OE NC GND
1 2 3
6 5 4
VDD
CLK– CLK+
Si531 (LVDS/LVPECL/CML)
OE GND
Preliminary Rev. 0.4 5/06
Copyright © 2006 by Silicon Laboratories
Si530/531
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Free Datasheet http://www.datasheet4u.com/
Si530/531
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Supply Voltage1 Symbol VDD Test Condition 3.3 V option 2.5 V option 1.8 V option Supply Current IDD Output enabled TriState mode Output Enable (OE)2 VIH VIL Operating Temperature Range TA Min 2.97 2.25 1.71 — — 0.75 x VDD — –40 Typ 3.3 2.5 1.8 90 60 — — — Max 3.63 2.75 1.89 — — — 0.5 85 mA V Units
V ºC
Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details. 2. OE pin includes a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
Table 2. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency1,2
Symbol fO
Test Condition LVPECL/LVDS/CML CMOS
Min
10 10 — –20 –50
Typ
— — ±1.5 — — — —
Max
945 160 — +20 +50 ±10 10
Units
MHz
Initial Accuracy
fi
Measured at +25 °C at time of shipping
ppm ppm ppm ms
Temperature Stability1,3 Aging Powerup Time4
∆f/fO
Frequency drift over projected 15 year life
fa tOSC
— —
Notes: 1. See Section 3. "Ordering Information" on page 6 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO.
2
Preliminary Rev. 0.4
Si530/531
Table 3. CLK± Output Levels and Symmetry
Parameter LVPECL Output Option1 Symbol VO
VOD VSE
Test Condition
mid-level swing (diff) swing (single-ended) mid-level swing (diff)
Min
VDD – 1.42 1.1 0.5 1.125 0.32
Typ
—
Max
VDD – 1.25 1.9 0.93 1.275 0.50
Units
V VPP VPP V VPP
— —
1.20 0.40
LVDS Output Option2
VO
VOD
CML Output Option2
VO VOD
mid-level swing (diff) IOH = 32 mA
IOL = 32 mA
— 0.70
0.8 x VDD
VDD – 0.75 0.95 — — — 1 —
— 1.20
VDD
V
VPP V
CMOS Output Option3
VOH VOL
— — — 45
0.4 350 — 55
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML CMOS with CL = 15 pF
ps ns %
Symmetry (duty cycle)
SYM
LVPECL: LVDS: CMOS:
VDD – 1.3 V (diff) 1.25 V (diff) VDD/2
Notes: 1. 50 Ω to VDD – 2.0 V. 2. Rterm = 100 Ω (differential). 3. CL = 15 pF
Table 4. CLK± Output Phase Jitter
Parameter Phase Jitter (RMS)* for FOUT > 500 MHz Phase Jitter (RMS)* for FOUT of 125 to 500 MHz Symbol Test Condition 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) 12 kHz to 20 MHz (OC-48) Min — — — Typ 0.27 0.30 0.50 Max — — — Units ps ps
φJ φJ
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Table 5. CLK± Output Period Jitter
Parameter Period Jitter* for FOUT < 160 MHz Symbol JPER Test Condition RMS Peak-to-Peak Min — — Typ 1 5 Ma.