Document
Preliminary Data Sheet
Specifications in this document are tentative and subject to change.
RX210 Group
Renesas MCUs
50-MHz 32-bit RX MCUs, 78 DMIPS, up to 512-KB flash memory, 12-bit AD, 10-bit DA, ELC, MPC, RTC, up to 9 comms interfaces; incorporating functions for IEC60730 compliance
R01DS0041EJ0050 Rev.0.50 Apr 15, 2011
Features
■ 32-bit RX CPU core Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle) Fast interrupt CISC Harvard architecture with 5-stage pipeline Variable-length instructions, ultra-compact code On-chip debugging circuit ■ Low-power design and architecture Operation from a single 1.62- to 5.5-V supply 1.62-V operation available (at up to 20 MHz) Deep software standby mode with RTC remaining usable Four low-power modes ■ On-chip flash memory for code, no wait states 50-MHz operation, 20-ns read cycle No wait states for reading at full CPU speed 128- to 512-Kbyte capacities User code programmable via the SCI Programmable at 1.62 V For instructions and operands ■ On-chip data flash memory Eight Kbytes, reprogrammable up to TBD times Erasing and programming impose no load on the CPU. ■ On-chip SRAM, no wait states 20- to 64-Kbyte size capacities ■ DMA DMACA: Incorporates four channels DTC: Four transfer modes ■ ELC Module operation can be initiated by event signals without going through interrupts. Modules can operate while the CPU is sleeping. ■ Reset and supply management Nine types of reset, including the power-on reset (POR) Low voltage detection (LVD) with voltage settings ■ Clock functions Frequency of external clock: Up to 20 MHz Frequency of the oscillator for sub-clock generation: 32.768 kHz PLL circuit input: 4 to 12.5 MHz On-chip low- and high-speed oscillators, dedicated onchip low-speed oscillator for the IWDT Generation of a dedicated 32.768-kHz clock for the RTC Clock frequency accuracy measurement circuit (CAC) ■ Real-time clock Adjustment functions (30 seconds, leap year, and error) Time capture function Time capture on event-signal input through external pins RTC capable of initiating return from deep software standby mode
PLQP0100KB-A PLQP0080KB-A PLQP0080JA-A PLQP0064KB-A PLQP0064GA-A 14 × 14 mm, 0.5-mm pitch 12 × 12 mm, 0.5-mm pitch 14 × 14 mm, 0.65-mm pitch 10 × 10 mm, 0.5-mm pitch 14 × 14 mm, 0.8-mm pitch
PTLG0100JA-A
7 × 7 mm, 0.65-mm pitch
■ Independent watchdog timer 125-kHz on-chip low-speed oscillator produces a dedicated clock signal to drive IWDT operation. ■ Useful functions for IEC60730 compliance Self-diagnostic and disconnection-detection functions for the AD converter, clock-frequency accuracymeasurement circuit, independent watchdog timer, functions to assist in RAM testing, etc. ■ Up to nine communications interfaces SCI with many useful functions (up to seven interfaces) Asynchronous mode, clock synchronous mode, smart card interface I2C bus interface: Transfer at up to 1 Mbps, capable of SMBus operation (1 interface) RSPI (1)
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■ External address space Four CS areas (4 × 16 Mbytes) 8- or 16-bit bus space is selectable per area ■ Up to 14 extended-function timers 16-bit MTU2: input capture, output capture, complementary PWM output, phase counting mode (6 channels) 8-bit TMR (4 channels) 16-bit compare-match timers (4 channels)
■ 12-bit A/D converter Capable of conversion within 1 μs Sample-and-hold circuits (for three channels) Three-channel synchronized sampling available Self-diagnostic function and analog input disconnection detection assistance function ■ 10-bit D/A converter ■ Analog comparator ■ Programmable I/O ports 5-V tolerant, open drain, input pull-up, switching of driving ability ■ MPC Multiple locations are selectable for I/O pins of peripheral functions ■ Temperature sensor ■ Operating temp. range -40 C to +85C
R01DS0041EJ0050 Rev.0.50 Apr 15, 2011
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
RX210 Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different packages. Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.
Table 1.1
Classification CPU
Outline of Specifications (1 / 3)
Module/Function CPU Description Maximum operating frequency: 50 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock.