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Si5517DU
Vishay Siliconix
N- and P-Channel 20 V (D-S) MOSFET
PowerPAK® ChipFET® Dual
D2
D2 6
D1 7
D1 8
5
1.9 mm
1 3.0 mm Top View
Marking code: EA
1
4 G2
3 S2
2 G1
S1
Bottom View
PRODUCT SUMMARY
N-CHANNEL P-CHANNEL
VDS (V) RDS(on) () at VGS = ± 4.5 V RDS(on) () at VGS = ± 2.5 V RDS(on) () at VGS = ± 1.8 V Qg typ. (nC) ID (A) a Configuration
20
-20
0.039
0.072
0.045
0.100
0.055
0.131
6
5.5
6
-6
N- and p-pair
FEATURES
• TrenchFET® power MOSFETs • Thermally enhanced PowerPAK ChipFET
package - Small footprint area - Low on-resistance - Thin 0.8 mm profile • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
APPLICATIONS
D1
S2
• Complementary MOSFET
for portable devices
G2
- Ideal for circuits
buck-boost G1
S1 N-Channel MOSFET
D2 P-Channel MOSFET
ORDERING INFORMATION
Package Lead (Pb)-free and halogen-free
PowerPAK ChipFET Si5517DU-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL N-CHANNEL
P-CHANNEL
Drain-source voltage Gate-source voltage
Continuous drain current (TJ = 150 °C)
Pulsed drain current Source-drain current diode current
Maximum power dissipation
Operating junction and storage temperature range Soldering recommendations (peak temperature) d, e
TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C
TC = 25 °C TA = 25 °C TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C
VDS VGS ID IDM IS
PD TJ, Tstg
20 ±8 6a 6a 7.2 b, c 5.8 b, c 20 6.9 1.9 b, c 8.3 5.3 2.3 b, c 1.5 b, c
-55 to +150 260
-20 ±8 -6 a -6 a -4.6 b, c -3.7 b, c -15 -6.9 -1.9 b, c 8.3 5.3 2.3 b, c 1.5 b, c
UNIT V
A
W °C
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum junction-to-ambient b, f Maximum junction-to-case (drain)
SYMBOL
t5s Steady state
RthJA RthJC
N-CHANNEL
TYP.
MAX.
45
55
12
15
P-CHANNEL
TYP.
MAX.
45
55
12
15
UNIT °C/W
Notes
a. Based on TC = 25 °C b. Surface mounted on 1" x 1" FR4 board c. t = 5 s d. See solder profile (www.vishay.com/doc?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 105 °C/W for both channels
S-81449-Rev. B, 23-Jun-08
1
Document Number: 73529
For technical questions, contact:
[email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com
Si5517DU
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
Static
Drain-source breakdown voltage VDS temperature coefficient VGS(th) temperature coefficient Gate-source threshold voltage
VDS VDS/TJ VGS(th)/TJ VGS(th)
VGS = 0 V, ID = 1 mA VGS = 0 V, ID = -1 mA
ID = 250 μA ID = -250 μA ID = 250 μA ID = -250 μA VDS = VGS, ID = 250 μA VDS = VGS, ID = -250 μA
Gate-body leakage
IGSS
VDS = 0 V, VGS = ± 8 V
Zero gate voltage drain current On-state drain current b
Drain-source on-state resistance b
Forward transconductance b Dynamic a
IDSS ID(on) RDS(on) gfs
VDS = 20 V, VGS = 0 V VDS = -20 V, VGS = 0 V VDS = 20 V, VGS = 0 V, TJ = 55 °C VDS = -20 V, VGS = 0 V, TJ = 55 °C VDS 5 V, VGS = 4.5 V VDS -5 V, VGS = -4.5 V VGS = 4.5 V, ID = 4.4 A VGS = -4.5 V, ID = -3.3 A VGS = 2.5 V, ID = 4.1 A VGS = -2.5 V, ID = -2.8 A VGS = 1.8 V, ID = 1.8 A VGS = -1.8 V, ID = -0.76 A VDS = 10 V, ID = 4.4 A VDS = -10 V, ID = -3.3 A
Input capacitance Output capacitance Reverse transfer capacitance
Total gate charge
Gate-source charge Gate-drain charge
Ciss Coss Crss
Qg
Qgs Qgd
N-channel VDS = 10 V, VGS = 0 V, f = 1 MHz
P-channel VDS = -10 V, VGS = 0 V, f = 1 MHz
VDS = 10 V, VGS = 8 V, ID = 4.4 A VDS = -10 V, VGS = -8 V, ID = -4.6 A VDS = 10 V, VGS = 4.5 V ID = 4.4 A VDS = -10 V, VGS = -4.5 V, ID = -1.8 A
N-channel VDS = 10 V, VGS = 4.5 V ID = 4.4 A
P-channel VDS = -10 V, VGS = -4.5 V, ID = -1.8 A
Gate resistance
Rg
f = 1 MHz
N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch
N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch
MIN.
20 -20
0.4 -0.4 20 -15 -
-
TYP. a MAX. UNIT
17 -20 -2.6 2.4 0.0320 0.0600 0.0370 0.0830 0.0455 0.1080 22 0.9
1 -1 100 -100 1 -1 10 -10 0.0390 0.0720 0.0450 0.1000 0.0550 0.1310 -
V mV/°C
V nA μA A
S
520
-
455
-
100
-
pF
105
-
60
-
65
-
10.5
16
9.1
14
6
9
5.5
8.5
nC
0.91
-
0.75
-
0.7
-
1.5
-
1.9
-
8
-
S-81449-Rev. B, 23-Jun-08
2
Document Number: 73529
For technical questions, contact: pmostechsu.