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SPICE Device Model Si1317DL
Vishay Siliconix
P-Channel 20 V (D-S) MOSFET
DESCRIPTION
The attached SPICE model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C to + 125 °C temperature ranges under the pulsed 0 V to 5 V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.
CHARACTERISTICS
• P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the - 55 °C to + 125 °C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics
SUBCIRCUIT MODEL SCHEMATIC
D
CGD
M2 G RG Gy + – ETCV Gx CGS M1
R1 3
DBD
S
Note This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to the appropriate datasheet of the same number for guaranteed specification limits.
Document Number: 67525 S11-0395-Rev. A, 14-Mar-11
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Datasheet pdf - http://www.DataSheet4U.net/
This datasheet is subject to change without notice. THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.DataSheet.co.kr
SPICE Device Model Si1317DL
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER Static Gate-Source Threshold Voltage Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltage Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = - 10 V, VGS = - 4.5 V, ID = - 1.4 A VDS = - 10 V, VGS = - 2.5 V, ID = - 1.4 A VDS = - 10 V, VGS = 0 V, f = 1 MHz 273 56 45 3.4 2.2 0.7 1 272 55 44 4.3 2.7 0.7 1 nC pF VGS(th) RDS(on) gfs VSD VDS = VGS, ID = - 250 μA VGS = - 4.5 V, ID = - 1.4 A VGS = - 2.5 V, ID = - 1.2 A VDS = - 5 V, ID = - 1.4 A IS = - 0.7 A 0.70 0.126 0.160 4.5 - 0.70 0.125 0.160 5 - 0.80 V S V SYMBOL TEST CONDITIONS SIMULATED MEASURED DATA DATA UNIT
Notes a. Pulse test; pulse width 300 μs, duty cycle 2 %. b. Guaranteed by design, not subject to production testing.
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Document Number: 67525 S11-0395-Rev. A, 14-Mar-11
Datasheet pdf - http://www.DataSheet4U.net/
This datasheet is subject to change without notice. THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.DataSheet.co.kr
SPICE Device Model Si1317DL
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA TJ = 2.