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IS64WV25616BLL Dataheets PDF



Part Number IS64WV25616BLL
Manufacturers ISSI
Logo ISSI
Description 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM
Datasheet IS64WV25616BLL DatasheetIS64WV25616BLL Datasheet (PDF)

IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM JULY 2022 FEATURES HIGH SPEED: (IS61/64WV25616ALL/BLL) • High-speed access time: 8, 10, 20 ns • Low Active Power: 85 mW (typical) • Low Standby Power: 7 mW (typical) CMOS standby LOW POWER: (IS61/64WV25616ALS/BLS) • High-speed access time: 25, 35, 45 ns • Low Active Power: 35 mW (typical) • Low Standby Power: 0.6 mW (typical) CMOS standby • Single power supply — Vdd 1.65V to 2.2V (IS61WV2.

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IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM JULY 2022 FEATURES HIGH SPEED: (IS61/64WV25616ALL/BLL) • High-speed access time: 8, 10, 20 ns • Low Active Power: 85 mW (typical) • Low Standby Power: 7 mW (typical) CMOS standby LOW POWER: (IS61/64WV25616ALS/BLS) • High-speed access time: 25, 35, 45 ns • Low Active Power: 35 mW (typical) • Low Standby Power: 0.6 mW (typical) CMOS standby • Single power supply — Vdd 1.65V to 2.2V (IS61WV25616Axx) — Vdd 2.4V to 3.6V (IS61/64WV25616Bxx) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and Automotive temperature support • Lead-free available DESCRIPTION The ISSI IS61WV25616Axx/Bxx and IS64WV25616Bxx are high-speed, 4,194,304-bit static RAMs organized as 262,144 words by 16 bits. It is fabricated using ISSI's high- performance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV25616Axx/Bxx and IS64WV25616Bxx are packaged in the JEDEC standard 44-pin 400mil SOJ, 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT CE OE CONTROL WE CIRCUIT UB LB 256K x 16 MEMORY ARRAY COLUMN I/O Copyright © 2022 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. H2 07/20/2022 IS61WV25616ALL/ALS, IS61W.


IS61WV25616BLS IS64WV25616BLL IS64WV25616BLS


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