256Mb (8Mx32bit) Mobile DDR SDRAM
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256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O
Specification of 256Mb (8Mx32bit) Mobile DDR ...
Description
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256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O
Specification of 256Mb (8Mx32bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of 2,097,152 x32
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Apr. 2009 1
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256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O
Document Title 256MBit (4Bank x 2M x 32bits) MOBILE DDR SDRAM Revision History
Revision No.
0.1 0.2 1.0 1.1 1.2 Initial Draft IDD Specification updated The final version Correct Part No. (page 3) Insert DDR370 DC/AC Characteristics
History
Draft Date
May 2008 May 2008 Nov. 2008 Mar. 2009 Apr. 2009
Remark
Preliminary Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Apr. 2009 2
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Mobile DDR SDRAM 256Mbit (8M x 32bit) H5MS2622JFR Series H5MS2532JFR Series
FEATURES SUMMARY
● Mobile DDR SDRAM
clock cycle
● MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM)
- Double data rate architecture: two data transfer per
● Mobile DDR SDRAM INTERFACE
- x32 bus width - Multiplexed Address (Row address and Column address)
● CAS LATENCY
- Programmable CAS la...
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