H5MS1222EFP

www.DataSheet4U.net 128Mbit MOBILE DDR SDRAM based on 1M x 4Bank x32 I/O Specification of 128M (4Mx32bit) Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 1,048,576 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Jun. 2008 1 www.DataSheet4U.net Mobile DDR SDRAM 128Mbit (4M x 32bit) H5MS1222EFP Series Document Title 128MBit (4Bank x 1M x 32bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 - Initial Draft - Define IDD specification - Correct tREFi specification - Modify IDD values -. Modify IDD Values(p22,p23) , AC Characteristics(p.24) History Draft Date Sep. 2007 Feb. 2008 May. 2008 Jun. 2008 Jun. 2008 Remark Preliminary Preliminary Preliminary Preliminary Rev 1.0 / Jun. 2008 2 www.DataSheet4U.net Mobile DDR SDRAM 128Mbit (4M x 32bit) H5MS1222EFP Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS5B2ALFP - Multiplexed Address (Row address and Column address) BURST LENGTH SUPPLY VOLTAGE - 1.8V device: VDD and VDDQ = 1.7V to 1.95V MEMORY CELL ARRAY - 128Mbit (x32 device) = 1M x 4Bank x 32 I/O DATA STROBE - x32 device: DQS0 ~ DQS3 - Bidirectional, data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver - Data and data mask re...