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ICS9LPRS545 Dataheets PDF



Part Number ICS9LPRS545
Manufacturers Integrated Circuit Solution
Logo Integrated Circuit Solution
Description 48-pin CK505
Datasheet ICS9LPRS545 DatasheetICS9LPRS545 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS9LPRS545 Datasheet 48-pin CK505 for Intel Systems Recommended Application: 48-pin Low Cost CK505 w/fully integrated VREG and series resistors on differential outputs Output Features: • Integrated Series Resistors on differential outputs • 2 - CPU differential push-pull pairs • 4 - SRC differential push-pull pairs • 1 - CPU/SRC selectable differential push-pull pair • 1 - SRC/DOT selectable differential push-pull pair • 1- SRC/Stop_Inputs selectable different.

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Integrated Circuit Systems, Inc. ICS9LPRS545 Datasheet 48-pin CK505 for Intel Systems Recommended Application: 48-pin Low Cost CK505 w/fully integrated VREG and series resistors on differential outputs Output Features: • Integrated Series Resistors on differential outputs • 2 - CPU differential push-pull pairs • 4 - SRC differential push-pull pairs • 1 - CPU/SRC selectable differential push-pull pair • 1 - SRC/DOT selectable differential push-pull pair • 1- SRC/Stop_Inputs selectable differential push-pull pair • 1 - 25MHz SE1 output for Wake-on-Lan applications • 3 - PCI, 33MHz • 1 - USB, 48MHz • 1 - REF, 14.31818MHz Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/-100ppm frequency accuracy on all clocks Features/Benefits: • Supports spread spectrum modulation, default is 0.5% down spread • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Not recommended for new designs. The last time buy date for this product is 5/19/2011. Please refer to PDN K-10-18. Table 1: CPU Frequency Select Table FSLC B0b7 0 0 0 0 1 1 1 1 2 FSLB B0b6 0 0 1 1 0 0 1 1 1 FS LA B0b5 0 1 0 1 0 1 0 1 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 SRC MHz PCI MHz REF MHz USB MHz DOT MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Pin Configuration PCI0/CR#_A VDDPCI PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOT96T_LPR/SRCT0_LPR DOT96C_LPR/SRCC0_LPR GND VDD SE1 GND SRCT2_LPR/SATAT_LPR SRCC2_LPR/SATAC_LPR GNDSRC SRCT3_LPR/CR#_C SRCC3_LPR/CR#_D VDDSRC_IO SRCT4_LPR SRCC4_LPR CPU_STOP#/SRCC5_LPR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SCLK SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0_LPR CPUC0_LPR GNDCPU CPUT1_LPR_F CPUC1_LPR_F VDDCPU_IO CPUT2_ITP_LPR/SRCT8_LPR CPUC2_ITP_LPR/SRCC8_LPR VDDSRC_IO SRCT7_LPR/CR#_F SRCC7_LPR/CR#_E GNDSRC VDDSRC PCI_STOP#/SRCT5_LPR 48-SSOP/TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor 1479A—07/28/09 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. www.DataSheet4U.net 9LPRS545 Integrated Circuit Systems, Inc. ICS9LPRS545 Datasheet SSOP/TSSOP Pin Description PIN # 1 2 3 PIN NAME PCI0/CR#_A VDDPCI PCI4/SRC5_EN TYPE DESCRIPTION 4 5 6 7 8 9 10 PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOT96T_LPR/SRCT0_LPR 3.3V PCI clock output or CR#_A input. Default is PCI0. To configure this pin as CR#_A, the PCI output must first be disabled in Byte 2, bit 0. I/O Byte 5, bit 7: 0 = PCI0 enabled (default), 1= CR#_A enabled. Byte 5, bit 6: 0 = CR#_A controls SRC0 (default), 1= CR#_A# controls SRC2. PWR Power supply for PCI clocks, nominal 3.3V 3.3V PCI clock output / SRC5 enable strap. On powerup, the logic value on this pin determines if SRC5 or CPU_STOP#/PCI_STOP# is enabled. The latched value controls the pin function as follows I/O 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. I/O 0 =SRC8/SRC8# 1 = ITP/ITP# PWR Ground pin for the PCI outputs PWR Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / I/O Fixed 48MHz USB clock output. 3.3V. PWR Ground pin for the 48MHz outputs PWR Power pin for the DOT96 clocks, nominal 1.05V to 3.3V. True clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is SRCT0. After powerup, this pin function may be changed to DOT96T via SMBus Byte 1, bit 7 as follows: OUT 0= SRC0T 1=DOT96T Complementary clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is SRC0C. After powerup, this pin function may be changed to DOT96C via SMBus Byte 1, bit 7 as follows: OUT 0= SRC0C 1=DOT96C PWR Ground pin. PWR Power supply, nominal 3.3V OUT CK505 Singled Ended Output 1. 3.3V. PWR Ground pin. True clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor to OUT GND needed. Complementa.


2N5345A ICS9LPRS545 BC158


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