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K7K3218U2C Dataheets PDF



Part Number K7K3218U2C
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 1Mx36 & 2Mx18 DDRII CIO b2 SRAM
Datasheet K7K3218U2C DatasheetK7K3218U2C Datasheet (PDF)

K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM 36Mb DDRII+ SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS W.

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K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM 36Mb DDRII+ SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. www.DataSheet4U.com -1- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C Document Title 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM 1Mx36-bit, 2Mx18-bit DDRTM II+ CIO b2 SRAM Revision History Rev. No. 1.0 History 1. First Release Draft Date Aug. 28, 2008 Remark Final www.DataSheet4U.com -2- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM 1Mx36-bit, 2Mx18-bit DDRII CIO b2 SRAM FEATURES • 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide output data valid window and future freguency scaling. • I/O Supply Voltage 1.5V+0.1V/-0.1V • Pipelined, double-data rate operation. • Common data input/output bus . • HSTL I/O • Full data coherency, providing most current data. • Synchronous pipeline read with self timed late write. • Read latency : 2.5 clock cycles • Registered address, control and data input/output. • DDR(Double Data Rate) Interface on read and write ports. • Fixed 2-bit burst for both read and write operation. • Clock-stop supports to reduce current. • Two input clocks(K and K) for accurate DDR timing at clock rising edges only. • Two echo clocks (CQ and CQ) to enhance output data traceability. • Data Valid pin(QVLD) supported • Single address bus. • Byte write (x18, x36) function. • Simple depth expansion with no data contention. • Programmable output impedance(ZQ). • JTAG 1149.1 compatible test access port. • 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm Organization Part Number K7K3236U2C-F(E)C(I)45 X36 K7K3236U2C-F(E)C(I)40 K7K3236U2C-F(E)C(I)33 K7K3218U2C-F(E)C(I)45 X18 K7K3218U2C-F(E)C(I)40 K7K3218U2C-F(E)C(I)33 Cycle Access Unit Time Time 2.22 2.5 3.0 2.22 2.5 3.0 0.45 0.45 0.45 0.45 0.45 0.45 ns ns ns ns ns ns * -F(E)C(I) F(E) [Package type] : E-Pb Free, F-Pb C(I) [Operating Temperature] : C-Commercial, I-Industrial FUNCTIONAL BLOCK DIAGRAM 36 (or 18) DATA REG 36 (or 18) 19 (or 20) WRITE/READ DECODE WRITE DRIVER 72 (or 36) SENSE AMPS 1Mx36 (2Mx18) MEMORY ARRAY 36 (or 18) OUTPUT REG ADDRESS 19 (or 20) OUTPUT SELECT ADD REG OUTPUT DRIVER 36 (or 18) LD R/W BWX DQ QVLD CQ, CQ 4(or 2) CTRL LOGIC K K (Echo Clock out) CLK GEN SELECT OUTPUT CONTROL www.DataSheet4U.com Notes: 1. Numbers in ( ) are for x18 device Doff DDR SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology. -3- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 NC/SA* DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 SA DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA QVLD NC 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 NC/SA* NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI PIN CONFIGURATIONS(TOP VIEW) K7K3236T2C(1Mx36) Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb, 2A for 144Mb . 2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35. PIN NAME SYMBOL K, K QVLD CQ, CQ Doff SA DQ0-35 PIN NUMBERS 6B, 6A 6P 11A, 1A 1H 3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R 2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F 11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L 3M,10M,11M,2N,3N,11N,3P,10P,11P 4A 8A 7B,7A,5A,5B 2H,10H 11H 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L, 4M-8M,4N,8N 10R 11R 2R 1R 2A,10A,1B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E, 1F,9F,10F,1G,9G,10G,1J,2J,9J,1.


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