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ASAHI KASEI
AK2301A
AK2301A
3.3V Single channel PCM CODEC LSI
GENERAL DESCRIPTION The AK2301A is a single channel PCM CODEC for speech processing 8kHz sampling PCM data by DSP. The AK2301A interfaces with 14bit linear data (16bit format). It includes Band limiting filter, A/D and D/A converter, and universal op-amps for construction of the output filter. All functions are provided in small 24pin VSOP package and it is good for reducing the mounting space. PACKAGE - 24pin VSOP ・Pin to pin 7.9mm x 7.6mm ・Pin pitch 0.65mm FEATURE
- Single PCM CODEC and filtering - Mute function - PCM interface; 14bits linear data - Long
systems
(16bit format, serial interface) Frame / Short Frame are selected automatically - PCM data rate 256kHz/512kHz - Op-Amp for the external gain adjustment - Dual universal op-amps - Single power supply voltage +3.3±0.3V - Low power consumption - Small package
BLOCK DIAGRAM
GST VFTN VFTP AMPT
AAF
A/D
PCM I/F VR VFR GSR Internal Main Clock BGREF AMP1 AMP2 SMF AMPR D/A
CODEC Core
DX DR FS BCLK
PLL PLLC MUTEN RSTN TEST1 TEST2 TEST3 AMP2I
TAGND VREF VDD VSS www.DataSheet4U.com
AK2301A
AMP1O AMP1I AMP2O
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CONTENT
AK2301A
ITEMS -
PAGE
BLOCK DIAGRAM …………………………………… 1 PIN CONDITION……………………………………… 3 PIN FUNCTION……………………………………….. 4 ABSOLUTE MAXIMUM RATINGS………………… 5 RECOMMENDED OPERATING CONDITIONS…... 5 ELECTRICAL CHARACTERISTICS………………...5 PACKAGE INFORMATION…………………………. 10 PIN ASSIGNMENT…………………………………… 11 MARKING……………..………………………………. 11 CIRCUIT DESCRIPTION….………………………. 12 FUNCTIONAL DESCRIPTION……………………… 13 PCM CODEC………….…………………………. 13 PCM INTERFACE…………...…………………... 14 Long Frame / Short Frame…....……………... 14 MUTE……………………………….…………….. 16 RESET SEQUENCE……………………….……. 17 Universal op-amps……………………………. 18 APPLICATION CIRCUIT EXAMPLE ………………. 19
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PIN CONDITION AC load (MAX.) DC load (MIN.)
Output status (mute)
AK2301A
Pin#
15 16 14 7 8 9 6 19 5 3 2 4 23 22 18
Name
VFTN VFTP GST GSR VFR VR VDD VSS FS BCLK DX DR MUTEN RSTN VREF
I/O
I I O O I O I I O I I I O
Pin type
Analog Analog Analog Analog Analog Analog
Remarks
50pF 40pF
AC load 10kΩ (*1) AC load 8kΩ (*1) AC load 8KΩ (*1) Analog ground
40pF
CMOS CMOS CMOS CMOS CMOS CMOS Analog
50pF
Hi-Z
20 PLLC O Analog
17 TAGND 11 12 13 10 21 24 1 O Analog
- External capacitance 1.0µF or more - External capacitance 0.33µF±40% (Includes temperature characteristic) - External capacitance 1.0µF or more - 150uA load max
AMP2I AMP1I AMP1O AMP2O Test1 Test2 Test3
I I O O I I I
Analog Analog Analog Analog CMOS CMOS CMOS 40pF 40pF - - - AC load 8kΩ (*1) AC load 8kΩ (*1) - - -
- Tie to the VSS - Tie to the VSS - Tie to the VSS *1) AC load is a load against AGND. This value includes a feedback resistance of input/output op -amp.
- - -
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PIN FUNCTION Pin types NIN: Normal input AIN: Analog input Type Pin# Name 15 VFTN AIN AIN AOUT AOUT AIN AOUT PWR PWR NIN TOUT: Try state output AOUT: Analog output
AK2301A
16 VFTP 14 GST 7 GSR
8 9 6
VFR VR VDD
19 VSS 5 FS
3
BCLK
NIN TOUT NIN NIN NIN
2
DX
4
DR
23 MUTEN 22 RSTN
18 VREF
AOUT AOUT
20 PLLC
17 TAGND AOUT
11 AMP1I AIN 12 AMP2I www.DataSheet4U.com 13 AMP1O AOUT Output of the universal OP amp 10 AMP2O 21 TEST1 NIN Test pins (”H”=test mode) 24 TEST2 Please tie to VSS 1 TEAT3
PWR: Power / Ground Function Neagative analog input of the transmit OP amp. Diffelential or single amplifire is composed with the VFTP and the external registers. Transmit gain is defined by the ratio of the external registers. Positive analog input of the transmit OP amp. Output of the transmit OP amp. The external feedback resister is connected between this pin and VFTP. Output of the receive OP amp. Receive gain is defined by the ratio of the external registers. The differential output can be composed with using the VR. Negative analog input of the receive OP amp. Analog output of the D/A convertor equivalent to the received PCM code. Positive supply voltage +3.3V supply Ground (0V) Frame sync input This clock is input for the internal PLL which gerenates the internal system clocks. FS must be 8kHz clock which synchronized with BCLK and do not stop feeding. Bit clock of PCM data interface This clock defines the input/output timing of DX and RX. The frequency of BCLK should be 256kHz or 512kHz and do not stop feeding. Serial output of PCM data The PCM data is synchronized with BCLK. This output remains in the high impedance except for the period in which PCM data is transmitted. Serial input of PCM data The PCM data is synchronized with BCLK. Mute setting pin “L” level forces both A/D, D/A output to mute state. Reset signal input pin Reset operation starts by low input. This pin is used for the initialization at the power up. Please use MUTEN pin together to avoid the popping sound output until the LSI finish the initialaization after the power up.(Refer to P.13) Analo.