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STP4NA40FI

ST Microelectronics

N-CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

STP4NA40 STP4NA40FI N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR TYPE ST P 4NA 40 ST P 4NA 40 F I VDSS 400 V...


ST Microelectronics

STP4NA40FI

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Description
STP4NA40 STP4NA40FI N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR TYPE ST P 4NA 40 ST P 4NA 40 F I VDSS 400 V 400 V R DS( on) <2Ω <2Ω ID 4A 2.8 A s TYPICAL RDS(on) = 1.7 Ω s ± 30V GATE TO SOURCE VOLTAGE RATING s 100% AVALANCHE TESTED s REPETITIVE AVALANCHE DATA AT 100oC s LOW INTRINSIC CAPACITANCES s GATE GHARGE MINIMIZED s REDUCED THRESHOLD VOLTAGE SPREAD DESCRIPTION This series of POWER MOSFETS represents the most advanced high voltage technology. The optimized cell layout coupled with a new proprietary edge termination concur to give the device low RDS(on) and gate charge, unequalled ruggedness and superior switching performance. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE ABSOLUTE MAXIMUM RATINGS Symbol P ar amete r VD S Drain-source Voltage (VGS = 0) VDG R Drain-gate Voltage (RG S = 20 kΩ) VGS Gate-source Voltage ID Drain Current (continuous) at T c = 25 oC ID Drain Current (continuous) at T c = 100 oC IDM() Drain Current (pulsed) Ptot Total Dissipation at Tc = 25 oC Derating Factor VISO Insulation Withstand Voltage (DC) Tstg Storage Temperature Tj Max. Operating Junction Temperature () Pulse width limited by safe operating area November 1996 3 2 1 TO-220 3 2 1 ISOWATT220 INTERNAL SCHEMATIC DIAGRAM Val ue STP4NA40 STP4NA40FI 400 400 ± 30 4 2.8 2.5 1.7 16 16 80 40 0. 64 0. 32  2000 -65 to 150 150 Un...




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