AL2007LA

0.35µm 20MHZ-170MHZ FSPLL AL2007LA GENERAL DESCRIPTION The AL2007LA is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macrofunctions provide frequency multiplication capabilities. The output clock frequency Fout is related to the reference input clock frequency Fin by the following equation: Fout = ( m*Fin ) / ( p* 2S) Where, Fout is the output clock frequency. Fin is the reference input clock frequency. m,p and s are the values for programmable dividers. AL2007LA consists of a phase/Frequency Detector(PFD), a Charge Pump an External Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as shown in Figure1. FEATURES — 0.35um CMOS device technology — 3.3 Volt Single power supply — VCO frequency range: 60~170MHz — Output frequency range: 20~170MHz — Jitter ±150ps — Duty ratio 40% to 60% at 170MHz — Frequency changed by programmable divider — Power down mode IMPORTANT NOTICE Please contact SEC application engineer to confirm the proper selection of M,P,S value. FUNCTIONAL BLOCK DIAGRAM Fin Pre Divider P PFD Charge Pump Loop Filter (External) VCO Post Scaler S Fout Main Divider M Figure 1. Phase Lockd Loop Block Diagram 1 www.DataSheet.in AL2007LA 0.35µm 20MHZ-170MHZ FSPLL CORE PIN DESCRIPTION Name VDD VSS VDDA VSSA VBB FIN FILTER FOUT PWRDN I/O Type DP DG AP AG AB/DB DI AO DO DI I/O Pad vddd vssd vdda vssa vbba picc_bb poar50_bb pot12_bb picc...