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TC55VZM216AJJN/AFTN08,10,12
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT CMOS STATIC RAM DESCRIPTION
The TC55VZM216AJJN/AFTN is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode, and output enable ( OE ) provides fast memory access. Data byte control signals ( LB , UB ) provide lower and upper byte access. This device is well suited to cache memory applications where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible. The TC55VZM216AJJN/AFTN is available in plastic 44-pin SOJ and TSOP with 400mil width for high density surface assembly.
FEATURES
• Fast access time (the following are maximum values) TC55VZM216AJJN/AFTN08:8 ns TC55VZM216AJJN/AFTN10:10 ns TC55VZM216AJJN/AFTN12:12 ns Low-power dissipation (IDDO2) (the following are maximum values)
Cycle Time Operation (max) 8 140 10 130 12 120 ns mA
•
• • • • • •
Single power supply voltage of 3.3 V ± 0.3 V Fully static operation All inputs and outputs are LVTTL compatible Output buffer control using OE Data byte control using LB (I/O1 to I/O8) and UB (I/O9 to I/O16) Package: SOJ44-P-400-1.27 (AJJN) (Weight: 1.64 g typ) TSOP II44-P-400-0.80 (AFTN) (Weight: 0.45 g typ)
Standby:4 mA (both devices)
PIN ASSIGNMENT (TOP VIEW)
44 PIN SOJ 44 PIN TSOP
PIN NAMES
A0 to A17 A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VDD GND I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VDD I/O12 I/O11 I/O10 I/O9 NU A8 A9 A10 A11 A17 A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VDD GND I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VDD I/O12 I/O11 I/O10 I/O9 NU A8 A9 A10 A11 A17 I/O1 to I/O16
CE
Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Data Byte Control Inputs Power (+3.3 V) Ground Not Usable (Input)
WE
OE LB , UB
VDD GND NU
(TC55VZM216AJJN)
(TC55VZM216AFTN)
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TC55VZM216AJJN/AFTN08,10,12
BLOCK DIAGRAM
A0 A1 A4 A5 A8 A9 A13 A14 A15 A17
ROW ADDRESS BUFFER
ROW DECODER
MEMORY CELL ARRAY 1,024 × 256 × 16 (4,194,304)
VDD GND
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16
SENSE AMP DATA OUTPUT BUFFER CE COLUMN ADDRESS BUFFER CLOCK GENERATOR A2 A3 A6 A7 A10 A11 A12 A16 VALUE −0.5 to 4.6 −0.5* to 4.6 −0.5* to VDD + 0.5** 1.4 260 −65 to 150 −10 to 85 DATA INPUT BUFFER
COLUMN DECODER
WE
OE UB
LB
CE
CE
MAXIMUM RATINGS
SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Terminal Voltage Input/Output Terminal Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING UNIT V V V W °C °C °C
*: −1.5 V with a pulse width of 20% of tRC min (4 ns max) **: VDD + 1.5 V with a pulse width of 20% of tRC min (4 ns max)
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DATA OUTPUT BUFFER
DATA INPUT BUFFER
CE
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TC55VZM216AJJN/AFTN08,10,12
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
SYMBOL VDD VIH VIL PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage MIN 3.0 2.0 −0.3* TYP 3.3 MAX 3.6 VDD + 0.3** 0.8 UNIT V V V
*: −1.0 V with a pulse width of 20% of tRC min (4 ns max) **: VDD + 1.0 V with a pulse width of 20% of tRC min (4 ns max)
DC CHARACTERISTICS (Ta = 0° to 70°C, VDD = 3.3 V ± 0.3 V)
SYMBOL IIL ILO II (NU) PARAMETER Input Leakage Current VIN = 0 to VDD (Except NU pin) Output Leakage Current
CE = VIH or WE = VIL or OE = VIH, VOUT = 0 to VDD
TEST CONDITION
MIN −1 −1 −1 2.4 VDD − 0.2 tcycle = 8 ns tcycle = 10 ns tcycle = 12 ns tcycle = 8 ns tcycle = 10 ns tcycle = 12 ns
TYP
MAX 1
UNIT µA µA µA
1
Input Leakage Current VIN = 0 V (NU pin) Output High Voltage IOH = −2 mA IOH = −100 µA IOL = 2 mA IOL = 100 µA
CE = VIL, IOUT = 0 mA,
1 0.4 0.2 170 160 150
VOH
V
VOL
Output Low Voltage
IDDO1 Operating Current
OE = VIH,
Other Input = VIH/VIL
CE = 0.2 V, IOUT = 0 mA,
mA 140 130 120 55 mA 4
IDDO2
OE = VDD − 0.2 V,
Other Input = VDD − 0.2 V/0.2 V IDDS1 IDDS2 Standby Current
CE = VIH, Other Input = VIH or VIL
CE = VDD − 0.2 V, Other Input = VDD − 0.2 V or 0.2 V
CAPACITANCE (Ta = 25°C, f = 1 .0 MHz)
SYMBOL CIN CI/O Note: PARAMETER Input Capacitance Input/Output Capacitance VIN = GND VI/O = GND TEST CONDITION MAX 6 8 UNIT pF pF
This parameter is periodically sampled and is not 100% tested.
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TC55VZM216AJJN/AFTN08,10,12
OPERATING MODE
MODE
.