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NCP3123 Dataheets PDF



Part Number NCP3123
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Step-Down DC/DC Switching Regulator
Datasheet NCP3123 DatasheetNCP3123 Datasheet (PDF)

NCP3123 Dual 3.0 A, Step-Down DC/DC Switching Regulator The NCP3123 is a dual buck converter designed for low voltage applications requiring high efficiency. This device is capable of producing an output voltage as low as 0.8 V. The NCP3123 provides dual 3.0 A switching regulators with an adjustable 200 kHz − 2200 kHz switching frequency. The switching frequency is set by an external resistor. The NCP3123 also incorporates an auto−tracking and sequencing feature. Protection features include cy.

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NCP3123 Dual 3.0 A, Step-Down DC/DC Switching Regulator The NCP3123 is a dual buck converter designed for low voltage applications requiring high efficiency. This device is capable of producing an output voltage as low as 0.8 V. The NCP3123 provides dual 3.0 A switching regulators with an adjustable 200 kHz − 2200 kHz switching frequency. The switching frequency is set by an external resistor. The NCP3123 also incorporates an auto−tracking and sequencing feature. Protection features include cycle−by−cycle current limit and undervoltage lockout (UVLO). The NCP3123 comes in a 32−pin QFN package. Features • Input Voltage Range from 4.5 V to 13.2 V • 12 Vin to 5.0 Vout = 85% Efficiency Min @ 3.0 A • 200−2200 kHz Operation • Stable with Low ESR Ceramic Output Capacitor • 0.8 ±1.5% FB Reference Voltage • External Soft−Start • Out of Phase Operation of OUT1 & OUT2 • Auto−Tracking and Sequencing • Enable/Disable Capability • Hiccup Overload Protection • Low Shutdown Power (Iq < 100 mA) http://onsemi.com 1 32 QFN32 CASE 488AM MARKING DIAGRAM 1 NCP3123 AWLYYWWG G NCP3123 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 40 of this data sheet. Typical Applications • Set−Top Boxes, Portable Applications, Networking and Telecommunications • DSP/mP/FPGA Core VIN R_TRACK PG1 PG2 Enable Disable EN1 Enable Disable EN2 R14 R24 C3 GND PG1 PG2 EN1 SEQ1 EN2 SEQ2 TRACK1,2 AVIN FB1 RVIN NCP3123 SW1 VIN SW2 RT FB2 AGND COMP2 SS2 GND AGND COMP1 SS1 C12 RT C22 R23 R13 L11 D11 GND C1 GND L21 D21 GND C2 GND OUT1 R11 C11 R12 GND GND OUT2 R21 C21 R22 GND GND GND C23 GND C13 GND GND Figure 1. Typical Application Circuit © Semiconductor Components Industries, LLC, 2010 October, 2010 − Rev. 2 1 Publication Order Number: NCP3123/D COMP 1 FB 1 SS 1 TRACK 1 RT SEQ1 EN 1 EN 2 SEQ 2 SS 2 TRACK 2 COMP 2 FB 2 0 .9 . ref NCP3123 0 .1. ref Falling comp SHDN 1 pg 1 Delay HS protection 1 PG 1 VIN Error Amplifier EOTA 1 PWM 0o R CON TR OL LOGIC 1 S HS1 SW 1 Soft Start & Tracking Control (MUX1) 10 u 1V SS 1 10 u ref (0.8 V) OSCILLATOR FB1 0. 5V Overload Protection SHDN 1 Power Sequencing 1 Power Sequencing 2 Soft Start & Tracking Control (MUX2) SHDN 1 10u 10u Error Amplifier EOTA 2 SHDN2 1V SS 2 STAR TU P UVL O TH ER MAL SH U TD OWN AVIN Reference 0. 8V SHDN 2 SHDN1 SHDN2 FB2 0 .5V 180o Overload Protection S HS protection 2 PWM R CON TR OL LOGIC 2 GND 1 Signal Voltage AVIN AGND ref (0 .8V ) ref (0.8 V) GND 2 VIN HS 2 SW 2 0 .9 . ref pg 2 Delay 0 .1. ref Falling comp SHDN 2 PG 2 Figure 2. Block Diagram http://onsemi.com 2 NCP3123 PIN DESCRIPTION Pin Symbol 1, 31, 32 SW1 2−7 VIN 8 – 10 11 12 SW2 GND2 SS2 13 COMP2 14 AGND 15 FB2 16 RT 17 TRACK 2 18 TRACK 1 19 SEQ2 20 EN2 21 SEQ1 22 EN1 23 PG2 24 PG1 25 AVIN 26 FB1 27 AGND 28 COMP1 29 SS1 30 GND1 Exposed Pad (GND) Description Switch node of Channel 1. Connect an inductor between SW1 and the regulator output. Input power supply voltage pins. These pins should be connected together to the input signal supply voltage pin. Switch node of Channel 2. Connect an inductor between SW2 and the regulator output. Power ground for Channel 2 Soft−start control input for Channel 2. An internal current source charges an external capacitor connected to this pin to set the soft−start time. Compensation pin of Channel 2. This is the output of the error amplifier and inverting input of the PWM comparator. Analog ground; connect to GND1 and GND2. Feedback Pin. Used to set the output voltage of Channel 2 with a resistive divider from the output. Resistor select for the oscillator frequency. Connect a resistor from the RT pin to AGND to set the frequency of the master oscillator. Leave this pin floating, for 200 kHz operation. Tracking input for Channel 2. This pin allows the user to control the rise time of the second output. This pin must be tied high in the normal operation (except in the tracking mode). Tracking input for Channel 1. This pin allows the user to control the rise time of the first output. This pin must be tied high in the normal operation (except in the tracking mode). Sequence pin for Channel 2. I/O used in power sequencing. Connect SEQ to EN for normal operation of a standalone device. Enable input for Channel 2. Sequence pin for Channel 1. I/O used in power sequencing. Connect SEQ to EN for normal operation of a standalone device. Enable input for Channel 1. Power good, open−drain output of Channel 2. Output logic is pulled to ground when the output is less than 90% of the desired output voltage. Tied to an external pull−up resistor. Leave this pin floating, if not used. Power good, open−drain output of Channel 1. Output logic is pulled to ground when the output is less than 90% of the desired ou.


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