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MC74HCT125A Dataheets PDF



Part Number MC74HCT125A
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Quad 3-State Noninverting Buffer
Datasheet MC74HCT125A DatasheetMC74HCT125A Datasheet (PDF)

DATA SHEET www.onsemi.com Quad 3-State Noninverting Buffers High−Performance Silicon−Gate CMOS MC74HC125A, MC74HCT125A, MC74HC126A The MC74HC125A/MC74HCT125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The MC74HCT125A device inputs are compatible with Standard CMOS or TTL outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3−.

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DATA SHEET www.onsemi.com Quad 3-State Noninverting Buffers High−Performance Silicon−Gate CMOS MC74HC125A, MC74HCT125A, MC74HC126A The MC74HC125A/MC74HCT125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The MC74HCT125A device inputs are compatible with Standard CMOS or TTL outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3−state memory address drivers, clock drivers, and other bus−oriented systems. The devices have four separate output enables that are active−low (HC125A) or active−high (HC126A). Features • Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V (HC), 4.5 to 5.5 V (HCT) • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the JEDEC Standard No. 7 A Requirements • Chip Complexity: 72 FETs or 18 Equivalent Gates • −Q Suffix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 14 1 MARKING DIAGRAMS 14 SOIC−14 D SUFFIX CASE 751A 1 XXXXXXG AWLYWW 14 1 TSSOP−14 DT SUFFIX CASE 948G 14 XXX XXX ALYWG G 1 XXX A = Specific Device Code = Assembly Location WL, L = Wafer Lot Y = Year Ww, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 January, 2024 − Rev. 16 Publication Order Number: MC74HC125A/D MC74HC125A, MC74HCT125A, MC74HC126A A1 2 3 Y1 A1 2 3 Y1 OE1 1 5 A2 6 Y2 OE1 1 5 A2 6 Y2 OE2 4 9 A3 8 Y3 OE2 4 9 A3 8 Y3 OE3 10 12 A4 11 Y4 OE3 10 12 A4 11 Y4 13 OE4 PIN 14 = VCC PIN 7 = GND 125A − Active−Low Output Enables 13 OE4 PIN 14 = VCC PIN 7 = GND 126A − Active−High Output Enables Figure 1. Logic Diagrams OE1 1 A1 2 Y1 3 OE2 4 A2 5 Y2 6 GND 7 14 VCC 13 OE4 12 A4 11 Y4 10 OE3 9 A3 8 Y3 Figure 2. Pinout Diagram FUNCTION TABLE 125A Inputs Output A OE Y HL H LL L XH Z 126A Inputs Output A OE Y HH H LH L XL Z www.onsemi.com 2 MC74HC125A, MC74HCT125A, MC74HC126A MAXIMUM RATINGS Symbol Parameter Value Unit VCC VIN VOUT IIN IOUT ICC IIK IOK TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Input Clamp Current (VIN < 0 or VIN > VCC) Output Clamp Current (VOUT < 0 or VOUT > VCC) Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance (Note 1) SOIC−14 TSSOP−14 –0.5 to +6.5 –0.5 to VCC + 0.5 –0.5 to VCC + 0.5 ±20 ±35 ±75 ±20 ±20 –65 to +150 260 ±150 116 150 V V V mA mA mA mA mA _C _C _C _C/W PD Power Dissipation in Still Air at 25_C SOIC−14 1077 mW TSSOP−14 833 MSL Moisture Sensitivity Level 1 − FR Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ − 0.125 in VESD ESD Withstand Voltage (Note 2) Human Body Model >2000 V Charged Device Model N/A Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 76mm−by−114mm, 2−ounce copper trace no air flow per JESD51−7. 2. HBM tested to EIA / JESD22−A114−A. CDM tested to JESD22−C101−A. JEDEC recommends that ESD qualification to EIA/JESD22−A115A (Machine Model) be discontinued. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit MC74HC VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) (Note 3) 0 VCC V TA Operating Free−Air Temperature –55 +125 _C tr, tf Input Rise or Fall Time VCC = 2.0 V 0 VCC = 4.5 V 0 VCC = 6.0 V 0 1000 ns 500 400 MC74HCT VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V VIN, VOUT DC Input Voltage, DC Output Voltage (Referenced to GND) (Note 3) 0 VCC V TA Operating Free−Air Temperature –55 +125 _C tr, tf Input Rise or Fall Time 0 500 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 3. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. www.onsemi.com 3 MC74HC125A, MC74HCT125A, MC74HC126A DC ELECTRICAL CHARACTERISTICS (MC74HC125A, MC74HC1.


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