MC9S08DV128

www.DataSheet4U.com MC9S08DZ128 MC9S08DZ96 MC9S08DV128 MC9S08DV96 Data Sheet HCS08 Microcontrollers MC9S08DZ128 Rev. 1 5/2008 freescale.com www.DataSheet4U.com www.DataSheet4U.com MC9S08DZ128 Series Features 8-Bit HCS08 Central Processor Unit (CPU) 40-MHz HCS08 CPU (20-MHz bus) HC08 instruction set with added BGND instruction Support for up to 32 interrupt/reset sources Peripherals ADC — 24-channel, 12-bit resolution, 2.5 μs conversion time, automatic compare function, temperature sensor, internal bandgap reference channel ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; runs in stop3 mode MSCAN — CAN protocol - Version 2.0 A, B; standard and extended data frames; Support for remote frames; Five receive buffers with FIFO storage scheme; Flexible identifier acceptance filters programmable as: 2 x 32-bit, 4 x 16-bit, or 8 x 8-bit SCIx — Two SCIs supporting LIN 2.0 Protocol and SAE J2602 protocols; Full duplex non-return to zero (NRZ); Master extended break generation; Slave extended break detection; Wakeup on active edge SPIx — Up to two SPIs; Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting IICx — Up to two IICs; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; General Call Address; Interrupt driven byte-by-...