Document
Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
AD9553
FEATURES
Input frequencies from 8 kHz to 710 MHz Output frequencies up to 810 MHz LVPECL and LVDS (up to
200 MHz for CMOS output) Preset pin-programmable frequency translation ratios cover
popular wireline and wireless frequency applications, including xDSL, T1/E1, BITS, SONET, and Ethernet Arbitrary frequency translation ratios via SPI port On-chip VCO Accepts a crystal resonator for holdover applications Two single-ended (or one differential) reference input(s) Two output clocks (independently programmable as LVDS, LVPECL, or CMOS) SPI-compatible, 3-wire programming interface Single supply (3.3 V) Very low power: <450 mW (under most conditions) Small package size (5 mm × 5 mm) Exceeds Telcordia GR-253-CORE jitter generation, transfer, and tolerance specifications
APPLICATIONS
Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators
Extremely flexible frequency translation for SONET/SDH, Ethernet, Fibre Channel, DRFI/DOCSIS, and PON/EPON/GPON
Wireless infrastructure Test and measurement (including handheld devices)
GENERAL DESCRIPTION
The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two single-ended input reference signals or one differential input reference signal via the REFA and REFB inputs. The device supports holdover applications by allowing the user to connect a 25 MHz crystal resonator to the XTAL input.
The AD9553 is pin programmable, providing a matrix of standard input/output frequency translations from a list of 15 possible input frequencies to a list of 52 possible output frequency pairs (OUT1 and OUT2). The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency translations.
The AD9553 output drivers are compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9553 is implemented in a strictly CMOS process.
The AD9553 operates over the extended industrial temperature range of −40°C to +85°C.
REFA REFB XTAL
BASIC BLOCK DIAGRAM
AD9553
INPUT FREQUENCY
SOURCE SELECTOR
PLL
OUTPUT CIRCUITRY
PIN-DEFINED AND SERIAL PROGRAMMING
OUT2 OUT1
08565-001
Figure 1.
Rev. A
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AD9553* Product Page Quick Links
Last Content Update: 08/30/2016
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Evaluation Kits
• AD9553 Evaluation Board
Documentation
Data Sheet • AD9553: Flexible Clock Translator for GPON, Base
Station, SONET/SDH, T1/E1, and Ethernet Data Sheet
Software and Systems Requirements
• AD9553 Evaluation Board
Reference Materials
Product Selection Guide • RF Source Booklet
Design Resources
• AD9553 Material Declaration • PCN-PDN Information • Quality And Reliability • Symbols and Footprints
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AD9553
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Basic Block Diagram ........................................................................ 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3
Power Consumption .................................................................... 3 Logic Input Pins............................................................................ 3 Logic Output Pins......................................................................... 3 RESET Pin ..............................