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L6717 Dataheets PDF



Part Number L6717
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description High-efficiency hybrid AM2r2 controller
Datasheet L6717 DatasheetL6717 Datasheet (PDF)

www.DataSheet4U.com L6717 High-efficiency hybrid AM2r2 controller with I2C interface and embedded drivers Features ■ ■ Hybrid controller for both PVI and SVI CPUs Dual controller with 2 embedded high current drivers + 2 PWM for external driver for CPU CORE and 1 embedded high current driver for CPU NB Dynamic phase management (DPM) I2C interface to control offset, switching frequency and power management options Dual-edge asynchronous architecture with LTB technology® PSI management to increas.

  L6717   L6717


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www.DataSheet4U.com L6717 High-efficiency hybrid AM2r2 controller with I2C interface and embedded drivers Features ■ ■ Hybrid controller for both PVI and SVI CPUs Dual controller with 2 embedded high current drivers + 2 PWM for external driver for CPU CORE and 1 embedded high current driver for CPU NB Dynamic phase management (DPM) I2C interface to control offset, switching frequency and power management options Dual-edge asynchronous architecture with LTB technology® PSI management to increase efficiency in lightload conditions Dual overcurrent protection: Total and perphase Accurate voltage positioning Dual remote sense Feedback disconnection protection Programmable OV protection Oscillator internally fixed at 200 kHz externally adjustable LSLess startup to manage pre-biased output VFQFPN48 Package VFQFPN48 VFQFPN48 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Description L6717 is a hybrid CPU power supply controller embedding 2 high-current drivers for the CORE section and 1 driver for the NB section - requiring up to 2 external drivers when the CORE section works at 4 phase to optimize the application overall cost. I2C interface allows to manage offset both CORE and NB sections, switching frequency and dynamic phase management saving in component count, space and power consumption. Dynamic phase management automatically adjusts phase-count according to CPU load optimizing the system efficiency under all load conditions. The dual-edge asynchronous architecture is ® optimized by LTB technology allowing fast loadtransient response minimizing the output capacitor and reducing the total BOM cost. Fast protection against load over current is provided for both the sections. Feedback disconnection protection prevents from damaging the load in case of disconnections in the system board. L6717 is available in VFQFPN48 package. Applications ■ Hybrid high-current VRM / VRD for desktop / Server / Workstation / IPC CPUs supporting PVI and SVI interface High-density DC / DC converters ■ Table 1. Device summary Order codes Package VFQFPN48 Tape and reel Packing Tray L6717 L6717TR March 2010 Doc ID 17326 Rev 1 1/56 www.st.com 56 www.DataSheet4U.com Contents L6717 Contents 1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 5 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Hybrid CPU support and CPU_TYPE detection . . . . . . . . . . . . . . . . . . 19 5.1 5.2 5.3 5.4 PVI - parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SVI - serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 Set VID command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PWROK de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PSI_L and efficiency optimization at light-load . . . . . . . . . . . . . . . . . . . 24 HiZ management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Hardware jumper override - V_FIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Power manager I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 Power manager commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Overspeeding command (OVRSPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Overvoltage threshold adjustment (OV_SET) . . . . . . . . . . . . . . . . . . . . 30 Switching frequency adjustment (FSW_ADJ) . . . . . . . . . . . . . . . . . . . . 30 Droop function adjustment (DRP_ADJ) . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power management flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 Dynamic phase managemen.


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